Patent Assignment
Reel/Frame 051954/0661
Assignment of Assignor's Interest
Recorded: 2020-02-27
Pages: 3
Assignors
BISWAS, HIRANMAY
Executed: 2019-10-15
WANG, CHUNG-HSING
Executed: 2020-01-16
YANG, KUO-NAN
Executed: 2020-01-15
LIN, JIA HAN
Executed: 2020-01-15
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. VI, HSINCHU SCIENCE PARK, HSINCHU, 300, TAIWAN
Covered Property
(1)
Inter-Cell Leakage-Reducing Method of Generating Layout Diagram and System for Same