Patent Assignment
Reel/Frame 052214/0690
Assignment of Assignor's Interest
Recorded: 2020-03-24
Pages: 3
Assignors
LIN, SHIH-YAO
Executed: 2020-03-03
CHUANG, YI-LIN
Executed: 2020-03-05
CHEN, YIN-AN
Executed: 2020-03-05
HONG, SHIH FENG
Executed: 2020-03-05
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
NO.8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, TAIWAN
Covered Property
(1)
Method and System for Generating Layout Design of Integrated Circuit