Patent Assignment
Reel/Frame 053532/0476
Assignment of Assignor's Interest
Recorded: 2020-08-18
Pages: 3
Assignors
CHO, MIN-HYUNG
Executed: 2020-08-10
JEON, YOUNG-DEUK
Executed: 2020-08-10
KIM, SEONG MIN
Executed: 2020-08-10
Assignee
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
218, GAJEONG-RO, YUSEONG-GU, DAEJEON, 34129, KOREA, REPUBLIC OF
Covered Property
(1)
Memory Interface Circuit Including Output Impedance Monitor and Method of Calibrating Output Impedance Thereof