Patent Assignment
Reel/Frame 054206/0214
Assignment of Assignor's Interest
Recorded: 2020-10-29
Pages: 3
Assignors
HUANG, JING-HUEI
Executed: 2020-05-05
CHIU, YA-WEN
Executed: 2020-05-05
TAN, LUN-KUANG
Executed: 2020-05-05
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Property
(1)
Method for Reducing Line-End Space in Integrated Circuit Patterning