Patent Assignment
Reel/Frame 054824/0001
Assignment of Assignor's Interest
Recorded: 2021-01-06
Pages: 3
Assignors
DEATON, CRAIG FRANKLIN
Executed: 2021-01-05
KOMAR, CHRISTOPHER WILLIAM
Executed: 2020-12-21
LUNDGREN, LARS
Executed: 2020-12-21
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
System, Method, and Computer Program Product for Finding and Analyzing Deadlock Conditions Associated with the Formal Verification of an Electronic Circuit Design
Patent:
11,580,284 →
Application:
17/142,360 →