Patent Assignment
Reel/Frame 054947/0520
Assignment of Assignor's Interest
Recorded: 2021-01-19
Pages: 3
Assignor
YANG, JEN-HANG
Executed: 2021-01-15
Assignee
MEDIATEK INC.
NO. 1, DUSING RD. 1ST, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN
Covered Property
(1)
Processing Circuit Using Delay Element Coupled Between Control Terminal and Connection Terminal of Input Transistor for Hold Time Violation Immunity