Patent Assignment
Reel/Frame 055215/0567
Assignment of Assignor's Interest
Recorded: 2021-02-04
Pages: 3
Assignor
LIN, YIZHOU
Executed: 2020-11-06
Assignee
ARCADIA INNOVATION INCORPORATED
3072 SCOTT BLVD., SANTA CLARA, CALIFORNIA, 95054
Covered Property
(1)
Method to Reduce Full-Chip Timing Violation Through Time Budgeting in Integrated Circuit Design
Patent:
10,956,639 →
Application:
16/731,484 →
Related Assignments
(3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 4, 2021
From: TANG, JIAN
To: HIGON AUSTIN R & D CENTER CORPORATION
Reel/Frame 056193/0280 →
Assignment of Assignor's Interest
Feb 4, 2021
From: LIANG, HONGCHANG
To: HYGON INFORMATION TECHNOLOGY CO., LTD.
Reel/Frame 055139/0056 →
Assignment of Assignor's Interest
May 14, 2021
From: HIGON AUSTIN R&D CENTER CORPORATION
To: HYGON INFORMATION TECHNOLOGY CO., LTD.
Reel/Frame 056242/0468 →