Patent Assignment
Reel/Frame 055671/0612
SECURITY INTEREST
Recorded: 2020-12-24
Received: 2020-12-24
Pages: 235
Assignors
ATMEL CORPORATION
Executed: 2020-12-17
MICROCHIP TECHNOLOGY INCORPORATED
Executed: 2020-12-17
MICROSEMI CORPORATION
Executed: 2020-12-17
MICROSEMI STORAGE SOLUTIONS, INC.
Executed: 2020-12-17
SILICON STORAGE TECHNOLOGY, INC.
Executed: 2020-12-17
Assignee
WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
600 SOUTH FOURTH STREET, CTSO MAIL OPERATIONS, 7TH FLOOR, MINNEAPOLIS, MN, 55415, UNITED STATES
Covered Applications
(100)
BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER
App. No. 17/111,973
→
Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification
App. No. 17/111,218
→
METHOD AND SYSTEM FOR ENHANCED SPI COMMUNICATION
App. No. 17/109,315
→
FRONT-END CIRCUITRY FOR A DATA RECEIVER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/247,148
→
WORD LINE AND CONTROL GATE LINE TANDEM DECODER FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/104,385
→
METHOD AND APPARATUS FOR PHASE CURRENT BALANCING IN A MULTI-PHASE DC-TO-DC CONVERTER
App. No. 17/101,498
→
SELF-TIMED SENSING ARCHITECTURE FOR A NON-VOLATILE MEMORY SYSTEM
App. No. 17/095,331
→
TEMPERATURE COMPENSATION IN AN ANALOG MEMORY ARRAY BY CHANGING A THRESHOLD VOLTAGE OF A SELECTED MEMORY CELL IN THE ARRAY
App. No. 17/095,661
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SOURCE LINE PULLDOWN MECHANISM
App. No. 17/090,481
→
Regression Neural Network for Identifying Threshold Voltages to be Used in Reads of Flash Memory Devices
App. No. 17/089,891
→
OBFUSCATING CRYPTOGRAPHIC PARAMETERS USED IN ELLIPTICAL CURVE CRYPTOGRAPHY, AND RELATED SYSTEMS AND DEVICES
App. No. 17/086,007
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM
App. No. 17/082,956
→
INTEGRATED CIRCUIT (IC) PACKAGE WITH INTEGRATED INDUCTOR HAVING CORE MAGNETIC FIELD (B FIELD) EXTENDING PARALLEL TO SUBSTRATE
App. No. 17/074,848
→
CHARGE PUMP FOR USE IN NON-VOLATILE FLASH MEMORY DEVICES
App. No. 17/075,691
→
OVENS FOR ATOMIC CLOCKS AND RELATED METHODS
App. No. 16/949,222
→
SYSTEM AND METHOD FOR AUTO-RECOVERY IN LOCKSTEP PROCESSORS
App. No. 17/075,493
→
SYSTEM AND METHOD FOR MONITORING ANALOG FRONT-END (AFE) CIRCUITRY OF AN INDUCTIVE POSITION SENSOR
App. No. 17/075,157
→
TOUCH SENSOR SIGNAL INTEGRATION
App. No. 16/949,218
→
NON-VOLATILE MEMORY SYSTEM USING STRAP CELLS IN SOURCE LINE PULL DOWN CIRCUITS
App. No. 17/074,103
→
THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING AN OXIDE CAP LAYER AS A TFR ETCH HARDMASK
App. No. 17/071,584
→
THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING WET ETCHING OF A DIELECTRIC CAP
App. No. 17/071,356
→
THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING TFR CAP LAYER(S) AS AN ETCH STOP AND/OR HARDMASK
App. No. 17/071,442
→
Microcontroller with Increasing Protected Storage Area and Erase Protection
App. No. 63/091,333
→
FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS WITH ENHANCED FLOATING GATE TO FLOATING GATE CAPACITIVE COUPLING
App. No. 17/069,563
→
FOREIGN OBJECT DETECTION IN WIRELESS CHARGING SYSTEMS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/949,003
→
NEAR CONSTANT DELAY COMPARATOR FOR CLOSED-LOOP SYSTEM
App. No. 17/065,920
→
SYNCHRONIZATION OF SEQUENCE NUMBERS IN A NETWORK
App. No. 16/948,908
→
MOTOR-CURRENT CONTROL PROCESS FOR PERMANENT-MAGNET SYNCHRONOUS MOTORS AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/948,906
→
LOW COST POWER LINE MODEM
App. No. 17/037,919
→
EtherCAT Controllers
App. No. 17/030,439
→
LOW COST CRYPTOGRAPHIC ACCELERATOR
App. No. 16/948,480
→
PRECISION TUNING OF A PAGE OR WORD OF NON-VOLATILE MEMORY CELLS AND ASSOCIATED HIGH VOLTAGE CIRCUITS FOR AN ANALOG NEURAL MEMORY ARRAY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 17/024,410
→
SYSTEM AND METHOD FOR DATA SAMPLER DRIFT COMPENSATION
App. No. 17/022,480
→
METHOD OF FORMING A THREE-GATE NON-VOLATILE FLASH MEMORY CELL USING TWO POLYSILICON DEPOSITION STEPS
App. No. 17/021,678
→
Integrated Circuit (IC) Device Including A Force Mitigation System For Reducing Under-Pad Damage Caused By Wire Bond
App. No. 17/019,768
→
SYSTEMS AND METHODS FOR IMPROVED ROOT MEAN SQUARE (RMS) MEASUREMENT
App. No. 17/019,514
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TECHNIQUES FOR ROUTING SIGNALS USING INACTIVE SENSOR REGIONS OF TOUCH SENSORS AND RELATED SYSTEMS AND DEVICES
App. No. 16/948,270
→
PULSE-WIDTH MODULATION AND ARBITRATION FOR CONTEXTUAL AND UNIFORM LED ILLUMINATION IN USB APPLICATIONS
App. No. 17/013,978
→
MUTUAL AUTHENTICATION PROTOCOL FOR SYSTEMS WITH LOW-THROUGHPUT COMMUNICATION LINKS, AND DEVICES FOR PERFORMING THE SAME
App. No. 16/948,101
→
AUTONOMOUS TRANSMIT ERROR DETECTION OF SERIAL COMMUNICATION LINK RECEIVER-TRANSMITTER AND MICROCONTROLLER SYSTEM PERIPHERALS IMPLEMENTING THE SAME
App. No. 16/948,135
→
WEAR LEVELING IN EEPROM EMULATOR FORMED OF FLASH MEMORY CELLS
App. No. 17/006,550
→
Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
App. No. 17/005,139
→
SYSTEM ARCHITECTURE WITH SECURE DATA EXCHANGE
App. No. 16/947,937
→
METAL-INSULATOR-METAL (MIM) CAPACITOR
App. No. 16/999,358
→
Daisy Chain Streaming Mode
App. No. 16/998,097
→
DAISY CHAIN COMPLEX COMMANDS
App. No. 16/998,170
→
Daisy Chain Mode Entry Sequence
App. No. 16/998,050
→
VOLTAGE CONVERTERS WITH HYSTERETIC CONTROL
App. No. 16/947,785
→
PRE-PROCESSING OF DATA USING AUTONOMOUS MEMORY ACCESS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/947,688
→
ANALOG NEURAL MEMORY ARRAY STORING SYNAPSIS WEIGHTS IN DIFFERENTIAL CELL PAIRS IN ARTIFICIAL NEURAL NETWORK
App. No. 16/987,101
→
SYSTEMS AND METHODS FOR PROVISIONING WI-FI DEVICES
App. No. 16/986,447
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SUBSTANTIALLY CONSTANT ARRAY SOURCE IMPEDANCE WITH ADAPTIVE WEIGHT MAPPING AND DISTRIBUTED POWER
App. No. 16/986,812
→
GROUNDING TECHNIQUES FOR BACKSIDE-BIASED SEMICONDUCTOR DICE AND RELATED DEVICES, SYSTEMS AND METHODS
App. No. 16/947,530
→
ULTRA-PRECISE TUNING OF ANALOG NEURAL MEMORY CELLS IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 16/985,147
→
BASE ASSEMBLIES FOR KNOB ON DISPLAY DEVICES AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/947,327
→
KNOB ON DISPLAY DEVICES AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/947,326
→
Analog Switch For Transmitting High Voltage Signals Without Utilizing High Voltage Power Supplies
App. No. 16/933,983
→
Excitation Voltages for Touch Sensors
App. No. 16/932,901
→
TEMPERATURE COMPENSATION FOR MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM USED IN A DEEP LEARNING NEURAL NETWORK
App. No. 16/930,777
→
ANGULAR POSITION SENSOR AND ASSOCIATED METHOD OF USE
App. No. 16/927,553
→
PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 16/919,697
→
METHOD AND SYSTEM FOR RELIABLE AND SECURE MEMORY ERASE
App. No. 16/919,177
→
Host-Detecting USB Hub
App. No. 16/919,348
→
METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY PROGRAM ADJUSTMENT FOR MEMORY CELLS EXHIBITING RANDOM TELEGRAPH NOISE
App. No. 16/915,289
→
TECHNIQUES FOR WIDEBAND TOUCH SENSING AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/946,567
→
SELECTABLE INPUT BUFFERS OF GENERAL PURPOSE INPUTS AND MICROCONTROLLERS HAVING THE SAME
App. No. 16/946,500
→
Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide
App. No. 16/910,022
→
DMA-Scatter and Gather Operations for Non-Contiguous Memory
App. No. 16/906,262
→
CIRCUITS FOR BLEEDING SUPPLY VOLTAGE FROM A DEVICE IN A POWER DOWN STATE
App. No. 16/893,674
→
TIMER CIRCUIT WITH AUTONOMOUS FLOATING OF PINS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/946,067
→
CAPACITIVE LIQUID LEVEL SENSOR USING TRUE SIMULTANEOUS DIFFERENTIAL ACQUISITION IN PUSH PULL MODE
App. No. 62/704,895
→
Ratiometric Gain Error Calibration Schemes for Delta-Sigma ADCs with Capacitive Gain Input Stages
App. No. 16/879,917
→
Ratiometric Gain Error Calibration Schemes for Delta-Sigma ADCs with Programmable Gain Amplifier Input Stages
App. No. 16/879,941
→
FLASH MEMORY CELL AND ASSOCIATED HIGH VOLTAGE ROW DECODER
App. No. 16/879,663
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM
App. No. 63/024,351
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SOURCE LINE PULLDOWN MECHANISM
App. No. 63/022,551
→
Method of Forming Split Gate Memory Cells
App. No. 16/868,143
→
CIRCUIT AND METHODS FOR TRANSFERRING A PHASE VALUE BETWEEN CIRCUITS CLOCKED BY NON-SYNCHRONOUS CLOCK SIGNALS
App. No. 16/867,468
→
LOW POWER OBJECT DETECTION IN MULTI-COIL WIRELESS CHARGING SYSTEMS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/863,865
→
MEASURING CIRCUIT USING SWITCHED CAPACITORS FOR MEASURING VOLTAGE AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/861,089
→
DIGITAL DEMODULATION FOR WIRELESS POWER TRANSFER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/843,697
→
EMULATING COLLISIONS IN WIRED LOCAL AREA NETWORKS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/843,648
→
CONVERTERS FOR WIRELESS POWER TRANSFER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/843,726
→
Memory Pool Allocation for a Multi-Core System
App. No. 16/842,870
→
N-CHANNEL SERIAL PERIPHERAL COMMUNICATION, AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/840,143
→
Low Voltage Level Shifter For Integrated Circuit
App. No. 16/838,847
→
TECHNIQUES FOR FORMING INTEGRATED INDUCTOR-CAPACITOR OSCILLATORS AND RELATED METHODS, OSCILLATORS, SEMICONDUCTOR DEVICES, SYSTEMS-ON-CHIPS, AND OTHER SYSTEMS
App. No. 16/837,660
→
MESSAGE AUTHENTICATION WITH SECURE CODE VERIFICATION
App. No. 16/835,173
→
CIRCUITRY TO COMPENSATE FOR DATA DRIFT IN ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 16/830,733
→
PRECISE DATA TUNING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 16/829,757
→
METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY CELLS BY SCREENING MEMORY CELLS
App. No. 16/828,206
→
CIRCUIT TO CORRECT PHASE INTERPOLATOR ROLLOVER INTEGRAL NON-LINEARITY ERRORS
App. No. 16/827,691
→
DAISY-CHAINED SYNCHRONOUS ETHERNET CLOCK RECOVERY
App. No. 16/827,624
→
THERMAL MANAGEMENT PACKAGE AND METHOD
App. No. 16/816,874
→
PACKAGED SEMICONDUCTOR DIE WITH MICRO-CAVITY
App. No. 16/816,010
→
Non-volatile Memory Device With Stored Index Information
App. No. 16/813,317
→
Security of Embedded Devices Through a Device Lifecycle with a Device Identifier
App. No. 16/806,227
→
INTERFACING WITH A ONE-WIRE DEVICE THAT IS IN PARALLEL WITH A LOW-IMPEDANCE ELEMENT, AND RELATED SYSTEMS AND DEVICES
App. No. 16/803,865
→
Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices
App. No. 16/803,876
→
METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY LIMITING TIME GAP BETWEEN ERASE AND PROGRAM
App. No. 16/803,418
→