Patent Assignment
Reel/Frame 057276/0735
Assignment of Assignor's Interest
Recorded: 2021-08-24
Pages: 9
Assignors
EATON, MATTHEW DAVID
Executed: 2021-08-24
TAYLOR, GEORGE SIMON
Executed: 2021-08-17
LI, ZHUO
Executed: 2021-08-17
YOUREN, JAMES
Executed: 2021-08-18
XU, JI
Executed: 2021-08-18
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Identifying Redundant Logic Based on Clock Gate Enable Condition
Patent:
11,797,747 →
Application:
17/410,837 →