IP Library Assignment 059300/0571
Patent Assignment
Reel/Frame 059300/0571

Assignment of Assignor's Interest

Recorded: 2022-03-18 Pages: 15
Assignors
TAN, SIN S.
Executed: 2010-12-29
SRINIVASAN, SRIKANTH T.
Executed: 2010-12-27
RADHAKRISHNAN, SIVAKUMAR
Executed: 2010-12-20
JOURDAN, STEPHAN J.
Executed: 1997-10-13
LOOI, LILY PAO
Executed: 2022-03-09
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Dynamic and Idle Power Reduction Sequence Using Recombinant Clock and Power Gating
Patent: 8,782,456 →
Application: 12/978,452 →
Publication: US 2011/0296222
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 29, 2022
From: JOURDAN, STEPHAN J.
To: INTEL CORPORATION
Reel/Frame 059431/0005 →
Assignment of Assignor's Interest May 5, 2022
From: INTEL CORPORATION
To: MEDIATEK INC.
Reel/Frame 059828/0105 →