IP Library › Assignment 059863/0400
Patent Assignment
Reel/Frame 059863/0400

RELEASE OF SECURITY INTEREST

Recorded: 2022-03-10 Received: 2022-03-10 Pages: 262
Assignor
Assignees
MICROCHIP TECHNOLOGY INCORPORATED
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
SILICON STORAGE TECHNOLOGY, INC.
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
ATMEL CORPORATION
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
MICROSEMI CORPORATION
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
MICROSEMI STORAGE SOLUTIONS, INC.
2355 W CHANDLER BLVD, CHANDLER, AZ, 85224, UNITED STATES
Covered Applications (100)
BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER
App. No. 17/111,973
→
Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification
App. No. 17/111,218
→
METHOD AND SYSTEM FOR ENHANCED SPI COMMUNICATION
App. No. 17/109,315
→
FRONT-END CIRCUITRY FOR A DATA RECEIVER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 17/247,148
→
WORD LINE AND CONTROL GATE LINE TANDEM DECODER FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 17/104,385
→
METHOD AND APPARATUS FOR PHASE CURRENT BALANCING IN A MULTI-PHASE DC-TO-DC CONVERTER
App. No. 17/101,498
→
SELF-TIMED SENSING ARCHITECTURE FOR A NON-VOLATILE MEMORY SYSTEM
App. No. 17/095,331
→
TEMPERATURE COMPENSATION IN AN ANALOG MEMORY ARRAY BY CHANGING A THRESHOLD VOLTAGE OF A SELECTED MEMORY CELL IN THE ARRAY
App. No. 17/095,661
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ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SOURCE LINE PULLDOWN MECHANISM
App. No. 17/090,481
→
Regression Neural Network for Identifying Threshold Voltages to be Used in Reads of Flash Memory Devices
App. No. 17/089,891
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OBFUSCATING CRYPTOGRAPHIC PARAMETERS USED IN ELLIPTICAL CURVE CRYPTOGRAPHY, AND RELATED SYSTEMS AND DEVICES
App. No. 17/086,007
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ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM
App. No. 17/082,956
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INTEGRATED CIRCUIT (IC) PACKAGE WITH INTEGRATED INDUCTOR HAVING CORE MAGNETIC FIELD (B FIELD) EXTENDING PARALLEL TO SUBSTRATE
App. No. 17/074,848
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OVENS FOR ATOMIC CLOCKS AND RELATED METHODS
App. No. 16/949,222
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CHARGE PUMP FOR USE IN NON-VOLATILE FLASH MEMORY DEVICES
App. No. 17/075,691
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SYSTEM AND METHOD FOR AUTO-RECOVERY IN LOCKSTEP PROCESSORS
App. No. 17/075,493
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SYSTEM AND METHOD FOR MONITORING ANALOG FRONT-END (AFE) CIRCUITRY OF AN INDUCTIVE POSITION SENSOR
App. No. 17/075,157
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TOUCH SENSOR SIGNAL INTEGRATION
App. No. 16/949,218
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NON-VOLATILE MEMORY SYSTEM USING STRAP CELLS IN SOURCE LINE PULL DOWN CIRCUITS
App. No. 17/074,103
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THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING AN OXIDE CAP LAYER AS A TFR ETCH HARDMASK
App. No. 17/071,584
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THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING WET ETCHING OF A DIELECTRIC CAP
App. No. 17/071,356
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THIN FILM RESISTOR (TFR) FORMED IN AN INTEGRATED CIRCUIT DEVICE USING TFR CAP LAYER(S) AS AN ETCH STOP AND/OR HARDMASK
App. No. 17/071,442
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Microcontroller with Increasing Protected Storage Area and Erase Protection
App. No. 63/091,333
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FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS WITH ENHANCED FLOATING GATE TO FLOATING GATE CAPACITIVE COUPLING
App. No. 17/069,563
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FOREIGN OBJECT DETECTION IN WIRELESS CHARGING SYSTEMS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/949,003
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NEAR CONSTANT DELAY COMPARATOR FOR CLOSED-LOOP SYSTEM
App. No. 17/065,920
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SYNCHRONIZATION OF SEQUENCE NUMBERS IN A NETWORK
App. No. 16/948,908
→
MOTOR-CURRENT CONTROL PROCESS FOR PERMANENT-MAGNET SYNCHRONOUS MOTORS AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/948,906
→
LOW COST POWER LINE MODEM
App. No. 17/037,919
→
EtherCAT Controllers
App. No. 17/030,439
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LOW COST CRYPTOGRAPHIC ACCELERATOR
App. No. 16/948,480
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PRECISION TUNING OF A PAGE OR WORD OF NON-VOLATILE MEMORY CELLS AND ASSOCIATED HIGH VOLTAGE CIRCUITS FOR AN ANALOG NEURAL MEMORY ARRAY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 17/024,410
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SYSTEM AND METHOD FOR DATA SAMPLER DRIFT COMPENSATION
App. No. 17/022,480
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METHOD OF FORMING A THREE-GATE NON-VOLATILE FLASH MEMORY CELL USING TWO POLYSILICON DEPOSITION STEPS
App. No. 17/021,678
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SYSTEMS AND METHODS FOR IMPROVED ROOT MEAN SQUARE (RMS) MEASUREMENT
App. No. 17/019,514
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Integrated Circuit (IC) Device Including A Force Mitigation System For Reducing Under-Pad Damage Caused By Wire Bond
App. No. 17/019,768
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TECHNIQUES FOR ROUTING SIGNALS USING INACTIVE SENSOR REGIONS OF TOUCH SENSORS AND RELATED SYSTEMS AND DEVICES
App. No. 16/948,270
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PULSE-WIDTH MODULATION AND ARBITRATION FOR CONTEXTUAL AND UNIFORM LED ILLUMINATION IN USB APPLICATIONS
App. No. 17/013,978
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MUTUAL AUTHENTICATION PROTOCOL FOR SYSTEMS WITH LOW-THROUGHPUT COMMUNICATION LINKS, AND DEVICES FOR PERFORMING THE SAME
App. No. 16/948,101
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AUTONOMOUS TRANSMIT ERROR DETECTION OF SERIAL COMMUNICATION LINK RECEIVER-TRANSMITTER AND MICROCONTROLLER SYSTEM PERIPHERALS IMPLEMENTING THE SAME
App. No. 16/948,135
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WEAR LEVELING IN EEPROM EMULATOR FORMED OF FLASH MEMORY CELLS
App. No. 17/006,550
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Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
App. No. 17/005,139
→
SYSTEM ARCHITECTURE WITH SECURE DATA EXCHANGE
App. No. 16/947,937
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METAL-INSULATOR-METAL (MIM) CAPACITOR
App. No. 16/999,358
→
Daisy Chain Streaming Mode
App. No. 16/998,097
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Daisy Chain Mode Entry Sequence
App. No. 16/998,050
→
DAISY CHAIN COMPLEX COMMANDS
App. No. 16/998,170
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VOLTAGE CONVERTERS WITH HYSTERETIC CONTROL
App. No. 16/947,785
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PRE-PROCESSING OF DATA USING AUTONOMOUS MEMORY ACCESS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/947,688
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ANALOG NEURAL MEMORY ARRAY STORING SYNAPSIS WEIGHTS IN DIFFERENTIAL CELL PAIRS IN ARTIFICIAL NEURAL NETWORK
App. No. 16/987,101
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SYSTEMS AND METHODS FOR PROVISIONING WI-FI DEVICES
App. No. 16/986,447
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ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SUBSTANTIALLY CONSTANT ARRAY SOURCE IMPEDANCE WITH ADAPTIVE WEIGHT MAPPING AND DISTRIBUTED POWER
App. No. 16/986,812
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GROUNDING TECHNIQUES FOR BACKSIDE-BIASED SEMICONDUCTOR DICE AND RELATED DEVICES, SYSTEMS AND METHODS
App. No. 16/947,530
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ULTRA-PRECISE TUNING OF ANALOG NEURAL MEMORY CELLS IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 16/985,147
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BASE ASSEMBLIES FOR KNOB ON DISPLAY DEVICES AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/947,327
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KNOB ON DISPLAY DEVICES AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/947,326
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Excitation Voltages for Touch Sensors
App. No. 16/932,901
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Analog Switch For Transmitting High Voltage Signals Without Utilizing High Voltage Power Supplies
App. No. 16/933,983
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TEMPERATURE COMPENSATION FOR MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM USED IN A DEEP LEARNING NEURAL NETWORK
App. No. 16/930,777
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ANGULAR POSITION SENSOR AND ASSOCIATED METHOD OF USE
App. No. 16/927,553
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PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
App. No. 16/919,697
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METHOD AND SYSTEM FOR RELIABLE AND SECURE MEMORY ERASE
App. No. 16/919,177
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Host-Detecting USB Hub
App. No. 16/919,348
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METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY PROGRAM ADJUSTMENT FOR MEMORY CELLS EXHIBITING RANDOM TELEGRAPH NOISE
App. No. 16/915,289
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TECHNIQUES FOR WIDEBAND TOUCH SENSING AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/946,567
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SELECTABLE INPUT BUFFERS OF GENERAL PURPOSE INPUTS AND MICROCONTROLLERS HAVING THE SAME
App. No. 16/946,500
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Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide
App. No. 16/910,022
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DMA-Scatter and Gather Operations for Non-Contiguous Memory
App. No. 16/906,262
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CIRCUITS FOR BLEEDING SUPPLY VOLTAGE FROM A DEVICE IN A POWER DOWN STATE
App. No. 16/893,674
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TIMER CIRCUIT WITH AUTONOMOUS FLOATING OF PINS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/946,067
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CAPACITIVE LIQUID LEVEL SENSOR USING TRUE SIMULTANEOUS DIFFERENTIAL ACQUISITION IN PUSH PULL MODE
App. No. 62/704,895
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Ratiometric Gain Error Calibration Schemes for Delta-Sigma ADCs with Capacitive Gain Input Stages
App. No. 16/879,917
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Ratiometric Gain Error Calibration Schemes for Delta-Sigma ADCs with Programmable Gain Amplifier Input Stages
App. No. 16/879,941
→
FLASH MEMORY CELL AND ASSOCIATED HIGH VOLTAGE ROW DECODER
App. No. 16/879,663
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ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM
App. No. 63/024,351
→
ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SOURCE LINE PULLDOWN MECHANISM
App. No. 63/022,551
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Method of Forming Split Gate Memory Cells
App. No. 16/868,143
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CIRCUIT AND METHODS FOR TRANSFERRING A PHASE VALUE BETWEEN CIRCUITS CLOCKED BY NON-SYNCHRONOUS CLOCK SIGNALS
App. No. 16/867,468
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LOW POWER OBJECT DETECTION IN MULTI-COIL WIRELESS CHARGING SYSTEMS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/863,865
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MEASURING CIRCUIT USING SWITCHED CAPACITORS FOR MEASURING VOLTAGE AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/861,089
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DIGITAL DEMODULATION FOR WIRELESS POWER TRANSFER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/843,697
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EMULATING COLLISIONS IN WIRED LOCAL AREA NETWORKS AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/843,648
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CONVERTERS FOR WIRELESS POWER TRANSFER AND RELATED SYSTEMS, METHODS, AND DEVICES
App. No. 16/843,726
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Memory Pool Allocation for a Multi-Core System
App. No. 16/842,870
→
N-CHANNEL SERIAL PERIPHERAL COMMUNICATION, AND RELATED SYSTEMS, METHODS AND DEVICES
App. No. 16/840,143
→
Low Voltage Level Shifter For Integrated Circuit
App. No. 16/838,847
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TECHNIQUES FOR FORMING INTEGRATED INDUCTOR-CAPACITOR OSCILLATORS AND RELATED METHODS, OSCILLATORS, SEMICONDUCTOR DEVICES, SYSTEMS-ON-CHIPS, AND OTHER SYSTEMS
App. No. 16/837,660
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MESSAGE AUTHENTICATION WITH SECURE CODE VERIFICATION
App. No. 16/835,173
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CIRCUITRY TO COMPENSATE FOR DATA DRIFT IN ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 16/830,733
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PRECISE DATA TUNING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK
App. No. 16/829,757
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METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY CELLS BY SCREENING MEMORY CELLS
App. No. 16/828,206
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CIRCUIT TO CORRECT PHASE INTERPOLATOR ROLLOVER INTEGRAL NON-LINEARITY ERRORS
App. No. 16/827,691
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DAISY-CHAINED SYNCHRONOUS ETHERNET CLOCK RECOVERY
App. No. 16/827,624
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THERMAL MANAGEMENT PACKAGE AND METHOD
App. No. 16/816,874
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PACKAGED SEMICONDUCTOR DIE WITH MICRO-CAVITY
App. No. 16/816,010
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Non-volatile Memory Device With Stored Index Information
App. No. 16/813,317
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Security of Embedded Devices Through a Device Lifecycle with a Device Identifier
App. No. 16/806,227
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INTERFACING WITH A ONE-WIRE DEVICE THAT IS IN PARALLEL WITH A LOW-IMPEDANCE ELEMENT, AND RELATED SYSTEMS AND DEVICES
App. No. 16/803,865
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Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices
App. No. 16/803,876
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METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY LIMITING TIME GAP BETWEEN ERASE AND PROGRAM
App. No. 16/803,418
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