IP Library › Assignment 062166/0893
Patent Assignment
Reel/Frame 062166/0893

Assignment of Assignor's Interest

Recorded: 2022-12-21 Pages: 4
Assignors
LILAK, AARON D.
Executed: 2018-06-29
DEWEY, GILBERT
Executed: 2018-06-29
RACHMADY, WILLY
Executed: 2018-07-10
HOURANI, RAMI
Executed: 2018-07-11
BOJARSKI, STEPHANIE A.
Executed: 2018-07-10
MEHANDRU, RISHABH
Executed: 2018-06-29
PHAN, ANH
Executed: 2018-07-10
MANNEBACH, EHREN
Executed: 2018-06-29
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Techniques for Forming Gate Structures for Transistors Arranged in a Stacked Configuration on a Single Fin Structure
Application: 16/024,080 →
Publication: US 2020/0006331
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 12, 2018
From: LILAK, AARON D.; DEWEY, GILBERT; RACHMADY, WILLY; HOURANI, RAMI
To: INTEL CORPORATION
Reel/Frame 046335/0496 →