IP Library › Assignment 062214/0202
Patent Assignment
Reel/Frame 062214/0202

Assignment of Assignor's Interest

Recorded: 2022-12-23 Pages: 62
Assignor
QSIGMA INC. (CA)
Executed: 2022-09-23
Assignee
QSIGMA INC
8913 BASANITE AVENUE, DENTON, TEXAS, 76207
Covered Properties (50)
Computer for Amdahl-Compliant Algorithms Like Matrix Inversion
Method and apparatus emulating read only memories with combinatorial logic networks, and methods and apparatus generating read only memory emulator combinatorial logic networks
Application: 10/155,502 →
Publication: US 2003/0233219
Method and Apparatus for High Speed Calculation of Non-Linear Functions and Networks Using Non-Linear Function Calculations for Digital Signal Processing
Patent: 7,284,027 →
Application: 10/226,735 →
Publication: US 2003/0041083
Method and apparatus of dsp resource allocation and use
Application: 10/276,414 →
Publication: US 2006/0248311
Method and Apparatus for Narrow to Very Wide Instruction Generation for Arithmetic Circuitry
Patent: 7,584,234 →
Application: 10/678,570 →
Publication: US 2004/0073588
Method and Apparatus Supporting Non-Additive Calculations in Graphics Accelerators and Digital Signal Processors
Patent: 7,617,268 →
Application: 11/036,538 →
Publication: US 2005/0182811
Apparatus and Method for Implementing Floating Point Additive and Shift Operations
Patent: 8,069,200 →
Application: 11/380,613 →
Publication: US 2006/0248137
Method and Apparatus for High Speed Calculation of Non-Linear Functions and Networks Using Non-Linear Function Calculations for Digital Signal Processing
Patent: 8,041,756 →
Application: 11/856,737 →
Computer for Amdahl-Compliant Algorithms Like Matrix Inversion
Patent: 8,892,620 →
Application: 13/500,103 →
Publication: US 2012/0203814
Computer for Amdahl-Compliant Algorithms Like Matrix Inversion
Patent: 9,753,726 →
Application: 14/516,456 →
Publication: US 2015/0039866
Simultaneous Multi-Processor Apparatus Applicable to Acheiving Exascale Performance for Algorithms and Program Systems
Patent: 9,846,623 →
Application: 15/141,031 →
Publication: US 2017/0052857
Semantic and/or Compiler Compatible Simultaneous Multi-Processor Core and/or Core Module with a Superscalar Microprocessor
Application: 15/695,939 →
Simultaneous Multi-Processor Apparatus Applicable to Acheiving Exascale Performance for Algorithms and Program Systems
Application: 15/844,740 →
Publication: US 2018/0121291
Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods
Application: 16/154,293 →
Publication: US 2019/0108346
Simultaneous Multi-Processor Apparatus Applicable to Acheiving Exascale Performance for Algorithms and Program Systems
Application: 16/674,083 →
Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods
Application: 16/680,899 →
Method and apparatus of a digital arithmetic and memory circuit with coupled control system and arrays thereof
Application: 60/204,113 →
Method and apparatus of a digital arithmetic and memory circuit with coupled control system and arrays thereof
Application: 60/215,894 →
Method and apparatus of a digital arithmetic and memory circuit with coupled control system and arrays thereof
Application: 60/217,353 →
Method and apparatus of a digital arithmetic and memory circuit with coupled control system and arrays thereof
Application: 60/231,873 →
Method and apparatus of a DSP resource circuit
Application: 60/261,066 →
Method and apparatus of a DSP resource Circuit
Application: 60/282,093 →
Method and aparatus for high speed calculation of non-linear functions
Application: 60/314,411 →
64 Point FFT engine
Application: 60/325,093 →
Methods and apparatus compiling non-linear functions, matrices and instruction memories and the apparatus resulting therefrom
Application: 60/365,416 →
Method and apparatus providing time division multiplexed arithmetic resources for digital signal processing and emulation of instruction memories
Application: 60/402,346 →
Method and apparatus providing generation of a very long instruction word
Application: 60/454,755 →
Method and apparatus implementing and using at least one logarithmic calculator to optimize floating point performance in a graphics accelerator
Application: 60/470,100 →
Programmable building blocks for increased floating point throughput
Application: 60/536,745 →
High throughput shader datapath arthitecture using programmable floating point buidling blocks
Application: 60/562,493 →
Integrated function module for graphics accelerators
Application: 60/605,224 →
Method and apparatus for floating point additive circuitry
Application: 60/675,752 →
Apparatus and Method for Supporting at Least Matrix Inversion and Floating Point Finite Impulse Response Filters in Single Core and Multiple Core Chips and Multi-Chip Systems with Linear Performance Improvement
Application: 61/249,503 →
Apparatus and Method for Supporting Efficient Matrix Inversion and Floating Point Finite Impulse Response Filters in Single Core and Multiple Core Chips and Multi-Chip Systems with Linear Performance Improvement
Application: 61/301,945 →
Apparatus and Method for Supporting Efficient Matrix Inversion and Floating Point Finite Impulse Response Filters in Single Core and Multiple Core Chips and Multi-Chip Systems with Linear Performance Improvement
Application: 61/307,383 →
Computer Architecture Performing Block LU Decomposition at or above an Exaflop
Application: 62/207,432 →
Computer Architecture Performing Block LU Decomposition at or above an Exaflop
Application: 62/233,547 →
Circuitry and Circuit Operations Adapted to Operate Without Stalling Generation of Non-additive Terms and Semi-linear Multiplications
Application: 62/243,885 →
Apparatus and Methods for components and communications between components of a computer system
Application: 62/261,836 →
Simultaneous Multi-Processor Apparatus Applicable to Achieving Exascale Performance for Algorithms and Program Systems
Application: 62/328,470 →
Simultaneous Multi-Processor Cores Semantically Compatible with a Microprocessor, and or Transforming the Microprocessor’s Superscalar Instruction Interpreter into a Compile-time Utility
Application: 62/384,677 →
Semantically Compatible Cores with a Superscalar Microprocessor, Software Performing as a Superscalar Interpreter, as well as Systems, Computers, and Sensors Immune to Virus and RootKit Attacks
Application: 62/421,407 →
Apparatus Compatible with a Superscalar Microprocessor without hardware overhead for Superscalar interpretation, caching and thread collection, as well as Other Apparatus and Methods including Sparse Matrix Manipulation
Application: 62/453,985 →
Apparatus and Methods for Sparse Matrix Manipulation
Application: 62/466,333 →
Application Configurable DRAM Memory Management for High Performance Computers (HPC) and/or Big Data
Application: 62/539,526 →
Semantic and/or Compiler Compatible Simultaneous Multi-Processor Core and/or Core Module with a Superscalar Microprocessor, Implementing Vector and Pattern
Application: 62/569,566 →
Compatible Simultaneous Multi-Processor Core Module with a Multi-Core Superscalar Microprocessor Delivering a Teraflop Performance at 15 Watts or less
Application: 62/582,282 →
Methods concerned with Apparatus including Simultaneous Multi-Processor (SiMulPro) cores, core modules, opto-transceiver banks, and/or DRAM controllers operating at least 512 Gigabytes of DRAM
Application: 62/595,583 →
Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods
Application: 62/696,315 →
Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods
Application: 62/742,417 →
Related Assignments (12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 22, 2002
From: JENNINGS, EARLE WILLIS III; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 013229/0878 →
Assignment of Assignor's Interest Nov 12, 2002
From: JENNINGS, EARLE
To: QSIGMA, INC.
Reel/Frame 013872/0337 →
Assignment of Assignor's Interest Dec 27, 2004
From: JENNINGS, EARLE WILLIS III; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 015542/0363 →
Assignment of Assignor's Interest Oct 23, 2019
From: JENNINGS, EARLE
To: QSIGMA, INC.
Reel/Frame 050799/0806 →
Assignment of Assignor's Interest Oct 23, 2019
From: JENNINGS, EARLE
To: QSIGMA, INC.
Reel/Frame 050801/0155 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050867/0286 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050867/0367 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050867/0614 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050879/0182 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050867/0232 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050867/0137 →
Assignment of Assignor's Interest Oct 30, 2019
From: JENNINGS, EARLE; LANDERS, GEORGE
To: QSIGMA, INC.
Reel/Frame 050866/0486 →