Method and apparatus for narrow to very wide instruction generation for arithmetic circuitry
A method and apparatus for generating a wide instruction controlling at least one data processing resource, local to that data processing resource, by accessing a local wide instruction memory based upon a narrow instruction, to generate at least part of the wide instruction. The local wide instruction memory can be accessed on every instruction cycle to reconfigure the controlled data processing resource(s). The data processing resources preferably includes arithmetic resources acting on the logarithms of various data inputs to generate a spectrum of non-additive results. A preferred embodiment permits the narrow instruction to include a designator field, a first narrow field and a second narrow field. The designator field is used by the local wide instruction memories to select which of the first and second narrow fields to use in accessing the memory for controls of a specific resource. Use in a graphics shader with four datapath columns is shown. Another preferred use is shown in a Digital Signal Processor (DSP) is also shown.
1. An apparatus operating a first number of a logalu, each using a wide instruction, comprising:
a narrow instruction provided to a local wide instruction memory;
said local wide instruction memory at least partly creating said wide instruction in response to said narrow instruction;
said logalu receiving said wide instruction;
said logalu configured based upon said wide instruction to operate upon a second number of a log-operand;
wherein said first number is at least one; and
wherein said second number is at least two.
2. The apparatus of claim 1 , wherein said first number is at least two.
3. The apparatus of claim 2 , wherein said logalu receiving said wide instruction is further comprised, for each of said logalus: said logalu receiving said wide instruction.
4. The apparatus of claim 2 , wherein said wide instruction for at least two of said logalus is at least partly distinct.
5. The apparatus of claim 1 , wherein said narrow instruction is comprised of a designator field, a first narrow field and a second narrow field;
wherein said local wide instruction memory responding to said narrow instruction, is further comprised of:
a means for selecting from said first narrow field and said second narrow field based upon said designator field to provide a selected narrow instruction to said local wide memory; and
said local wide memory responding to said selected narrow instruction to at least partly create said wide instruction.
6. The apparatus of claim 5 , wherein the means for selecting is further comprised of:
presenting said designator field to a selection configuration circuit; and
said selection configuration circuit responding to said designator field to select from said first narrow field and said second narrow field to create said selected narrow instruction.
7. The apparatus of claim 6 , further comprising:
means for providing a configuration signal to said selection configuration circuit; and
means for altering a state in said selection configuration circuit based upon said configuration signal.
8. The apparatus of claim 7 , wherein said state resides in a selection configuration memory included in said selection configuration circuit.
9. The apparatus of claim 1 , further comprising:
means for providing said local wide instruction memory with a write instruction;
wherein said local wide instruction memory responding to said narrow instruction is at least partly altered based upon said write instruction.
10. A apparatus of generating a non-additive result based upon said second number of a log2 operand of claim 1 , comprising:
said apparatus of claim 1 operating said logalu;
means for providing said log-operands to said logalu;
said logalu responding to said log-operands and to said wide instruction to create a log-result presented to an exponential calculator; and
said exponential calculator responding to said log-result to create said non-additive result.
11. The apparatus of claim 10 , wherein said non-additive result includes a first multiplicative component and a second multiplicative component;
wherein said first multiplicative component is a member of the non-additive primitive collection based upon a first of said log-operands;
wherein said second multiplicative component is a member of said non-additive primitive collection based upon a second of said log-operands;
wherein said non-additive primitive collection based upon one of said log-operands includes:
an exponential of said one log-operand,
an exponential of a half of said one log-operand,
an exponential of a negative of said one log-operand,
an exponential of a negative of said half of said one log-operand,
an exponential of a double of said one log-operand, and
an exponential of a negative of said double of said one log-operand.
12. The apparatus of claim 11 , further comprising the step of:
a log-calculator providing said first log-operand based upon a first operand;
wherein said non-additive primitive collection based upon one of said log-operands includes:
an approximation of said first operand,
an approximation of a square root of said first operand,
an approximation of a multiplicative inverse of said first operand,
an approximation of a multiplicative inverse of said square root of said first operand,
an approximation of a square of said first operand, and
an approximation of a multiplicative inverse of said square of said first operand.
13. The apparatus of claim 12 , wherein said approximations satisfy a precision standard.
14. The apparatus of claim 13 , wherein said precision standard supports a member of the programming languages collection comprising: a version of Java, a version of C, a version of OpenGL, and a version of DirectX.