Patent Assignment
Reel/Frame 062712/0860
Assignment of Assignor's Interest
Recorded: 2023-02-15
Pages: 2
Assignors
POLASA, RAKESH KUMAR
Executed: 2023-01-25
PATEL, VINAY SADRHALLI NAGENDRA
Executed: 2023-01-25
PALIWAL, SHUBHAM
Executed: 2023-01-25
MANI, ALAGESAN
Executed: 2023-01-25
Assignee
SILICONCH SYSTEMS PVT LTD
#119, 2ND FLOOR, 3RD CROSS, 1ST PHASE, RELIABLE RESIDENCY, HARALUR, BANGALORE, KARNATAKA, 560102, INDIA
Covered Property
(1)
System and Method for Processor Debug Using Low-Bandwidth Interface with Configurable List of Skip and Loop Instructions
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.