Patent Assignment
Reel/Frame 063251/0587
Assignment of Assignor's Interest
Recorded: 2023-04-07
Pages: 3
Assignor
WU, PO-HSUEH
Executed: 2023-03-29
Assignee
MEDIATEK INC.
NO. 1, DUSING RD. 1ST, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN
Covered Property
(1)
Clock Adjustment Circuit Using Pattern Filter Circuit to Select Predetermined Data Patterns for Phase Error Detection Under Acquisition Mode and Tracking Mode and Associated Clock Adjustment Method