Assignment of Assignor's Interest

Recorded: 2023-07-05 Pages: 8

Assignors

DING, YI-XIAO

Executed: 2023-07-03

LIN, SHENG-EN DAVID

Executed: 2023-06-30

VISWANATHAN, NATARAJAN

Executed: 2023-06-30

ALPERT, CHARLES JAY

Executed: 2023-06-30

Assignee

CADENCE DESIGN SYSTEMS, INC.

2655 SEELY AVENUE, BUILDING 5, SAN JOSE, CALIFORNIA, 95134

Covered Property (1)

Insertion Delay and Area Tradeoff for Buffering Solution Selection in Clock Tree Synthesis

Patent: 12,339,701 →

Application: 18/347,298 →