Patent Assignment
Reel/Frame 064836/0363
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT.
Recorded: 2023-09-07
Received: 2023-09-07
Pages: 14
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(72)
METHOD OF IMPROVING PERFORMANCE OF DEVICES WITH QDS COMPRISING THIN METAL OXIDE COATINGS
App. No. 17/370,218
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 13/397,562
→
APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 13/212,986
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 13/117,500
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOUNTABLE INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/090,192
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/088,647
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/080,070
→
SEMICONDUCTOR PACKAGE SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF
App. No. 13/053,141
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
App. No. 13/039,311
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SACRIFICIAL PROTECTIVE LAYER TO PROTECT SEMICONDUCTOR DIE EDGE DURING SINGULATION
App. No. 13/029,936
→
METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD
App. No. 13/023,329
→
STRUCTURE FOR BUMPED WAFER TEST
App. No. 13/019,643
→
METHOD FOR MANUFACTURING PACKAGE SYSTEM INCORPORATING FLIP-CHIP ASSEMBLY
App. No. 12/976,753
→
PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/970,755
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/961,490
→
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING THE SAME
App. No. 12/950,591
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 12/912,467
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A THERMAL DISSIPATION PATH THROUGH RDL AND CONDUCTIVE VIA
App. No. 12/911,042
→
SEMICONDUCTOR WAFER HAVING THROUGH-HOLE VIAS ON SAW STREETS WITH BACKSIDE REDISTRIBUTION LAYER
App. No. 12/896,430
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULANT CONTAINMENT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/882,856
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
App. No. 12/882,083
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/859,049
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
App. No. 12/858,615
→
DISPOSABLE SHAKER
App. No. 12/867,789
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING B-STAGE CONDUCTIVE POLYMER OVER CONTACT PADS OF SEMICONDUCTOR DIE IN FO-WLCSP
App. No. 12/853,898
→
QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/827,864
→
INTEGRATED CIRCUIT SYSTEM WITH RECESSED THROUGH SILICON VIA PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/820,491
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AROUND BACK SURFACE AND SIDES OF SEMICONDUCTOR WAFER CONTAINING IPD STRUCTURE
App. No. 12/816,190
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/797,922
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/796,668
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMALLY CONDUCTIVE LAYER BETWEEN SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE
App. No. 12/794,612
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
App. No. 12/789,456
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DISCONTINUOUS ESD PROTECTION LAYERS BETWEEN SEMICONDUCTOR DIE
App. No. 12/780,295
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
App. No. 12/779,781
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/772,142
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/732,465
→
FUSIBLE I/O INTERCONNECTION SYSTEMS AND METHODS FOR FLIP-CHIP PACKAGING INVOLVING SUBSTRATE-MOUNTED STUD BUMPS
App. No. 12/731,354
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL MULTI-ROW ETCHED LEAD PACKAGE
App. No. 12/719,476
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD IN FAN-OUT LEVEL CHIP SCALE PACKAGE
App. No. 12/713,018
→
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
App. No. 12/643,180
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/635,695
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
App. No. 12/633,531
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COLUMN INTERCONNECT STRUCTURE TO REDUCE WAFER STRESS
App. No. 12/610,763
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/579,307
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING THERMALLY CONDUCTIVE LAYER IN INTERCONNECT STRUCTURE FOR HEAT DISSIPATION
App. No. 12/507,130
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE USING STUD BUMPS
App. No. 12/492,360
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADFRAME HAVING RADIAL-SEGMENTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,043
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,383
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,303
→
MAKING A SEMICONDUCTOR DEVICE HAVING CONDUCTIVE THROUGH ORGANIC VIAS
App. No. 12/406,038
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-OUT STRUCTURE WITH INTEGRATED PASSIVE DEVICE AND DISCRETE COMPONENT
App. No. 12/207,332
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/136,037
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE
App. No. 12/113,888
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STEP MOLD RECESS
App. No. 12/053,751
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK SPACER STRUCTURES
App. No. 12/050,797
→
SYSTEM FOR PEELING SEMICONDUCTOR CHIPS FROM TAPE
App. No. 12/018,065
→
MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION
App. No. 11/965,653
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR SHIELDING ELECTROMAGNETIC INTERFERENCE
App. No. 11/956,132
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE AND METHOD OF MANUFACTURE THEREOF
App. No. 11/950,216
→
WAFER LEVEL DIE INTEGRATION AND METHOD
App. No. 11/949,133
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE
App. No. 11/947,303
→
MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING INTERCONNECTS
App. No. 11/934,069
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
App. No. 11/843,649
→
INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM WITH ADHESIVELESS PACKAGE ATTACH
App. No. 11/769,691
→
ELECTRONIC SYSTEM WITH EXPANSION FEATURE
App. No. 11/750,715
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATING FEATURES
App. No. 11/694,921
→
INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY
App. No. 11/670,714
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLASHLESS LEADS
App. No. 11/670,899
→
DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM
App. No. 11/618,806
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MOLD FLASH PREVENTION TECHNOLOGY
App. No. 11/615,919
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER
App. No. 11/465,706
→
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
App. No. 10/921,376
→