Patent Assignment
Reel/Frame 065919/0824
Assignment of Assignor's Interest
Recorded: 2023-12-20
Pages: 4
Assignors
LI, JIAN-SING
Executed: 2021-06-28
YANG, JUNG-CHAN
Executed: 2021-06-28
CHEN, TING-YU
Executed: 2021-06-28
CHIANG, TING-WEI
Executed: 2021-06-28
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Property
(1)
Method of Designing an Integrated Circuit and System for Designing Integrated Circuit