IP Library Assignment 066430/0502
Patent Assignment
Reel/Frame 066430/0502

Assignment of Assignor's Interest

Recorded: 2024-02-09 Pages: 3
Assignors
TSALIAGKOS, DIMITRIOS
Executed: 2023-07-14
VOUDOURIS, PETROS
Executed: 2023-07-12
KERAMIDAS, GEORGIOS
Executed: 2023-07-14
Assignee
THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A.
PATRAS SCIENCE PARK, RION ACHAIAS, 26504, GREECE
Covered Property (1)
System and Method for Power and Latency Reduction by Inserting Instruction Hints in Processing Thread Execution Code in a Multithreaded Architecture
Application: 18/550,566 →
Publication: US 2025/0217145
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Change of Name Mar 6, 2026
From: THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A.
To: THINK SILICON SINGLE MEMBER P.C.
Reel/Frame 075032/0035 →
Assignment of Assignor's Interest Jun 9, 2026
From: THINK SILICON SINGLE MEMBER P.C. AND APPLIED MATERIALS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 075735/0803 →