TECHNIQUES FOR PIPELINING SINGLE THREAD INSTRUCTIONS TO IMPROVE EXECUTION TIME
A system and method for power and latency reduction in processing thread execution code in a multithreaded architecture is disclosed. The method includes: receiving a plurality of threads, each thread including a plurality of instructions for execution on a core of a plurality of cores of a processing circuitry; detecting in a first thread of the plurality of threads a plurality of subsequent independent instructions; and inserting into an instruction an instruction hint which when executed configures an instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions.
1 . A method for power and latency reduction in processing thread execution code in a multithreaded architecture, comprising:
receiving a plurality of threads, each thread including a plurality of instructions for execution on a core of a plurality of cores of a processing circuitry;
detecting in a first thread of the plurality of threads a plurality of subsequent independent instructions; and
inserting into an instruction an instruction hint which when executed configures an instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions.
2 . The method of claim 1 , further comprising:
generating the instruction to add a number to a hardcoded register, wherein the number indicates a number of the subsequent independent instructions.
3 . The method of claim 2 , further comprising:
serially executing a number of subsequent independent instructions which is equal to the number added to the hardcoded register.
4 . The method of claim 3 , wherein the hardcoded register is hardcoded to a zero value.
5 . The method of claim 1 , further comprising:
detecting in a second thread of the plurality of threads a value of a bit indicator, wherein the bit indicator indicates a number of subsequent instructions; and
serially executing the number of subsequent instructions.
6 . The method of claim 1 , further comprising:
executing an instruction of a second thread of the plurality of threads, in response to completing execution of the plurality of subsequent instructions.
7 . The method of claim 1 , further comprising:
executing a first instruction of the plurality of subsequent independent instructions at a first clock cycle; and
executing a second instruction of the plurality of subsequent independent instructions at a second clock cycle, wherein the first clock cycle immediately precedes the second clock cycle.
8 . The method of claim 1 , further comprising:
generating the instruction hint to include a predetermine bit set to a value indicating that a next instruction is an independent instruction.
9 . The method of claim 8 , further comprising:
detecting that the instruction is of a first category; and
setting a number of predetermined bits to a value which indicates a number of next independent instructions based on the first category.
10 . The method of claim 9 , further comprising:
executing the next independent instructions.
11 . A non-transitory computer-readable medium storing a set of instructions for power and latency reduction in processing thread execution code in a multithreaded architecture, the set of instructions comprising:
one or more instructions that, when executed by one or more processors of a device, cause the device to:
receive a plurality of threads, each thread including a plurality of instructions for execution on a core of a plurality of cores of a processing circuitry;
detect in a first thread of the plurality of threads a plurality of subsequent independent instructions; and
insert into an instruction an instruction hint which when executed configures an instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions.
12 . A system for power and latency reduction in processing thread execution code in a multithreaded architecture comprising:
a processing circuitry; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
receive a plurality of threads, each thread including a plurality of instructions for execution on a core of a plurality of cores of a processing circuitry;
detect in a first thread of the plurality of threads a plurality of subsequent independent instructions; and
insert into an instruction an instruction hint which when executed configures an instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions.
13 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
generate the instruction to add a number to a hardcoded register, wherein the number indicates a number of the subsequent independent instructions.
14 . The system of claim 13 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
serially execute a number of subsequent independent instructions which is equal to the number added to the hardcoded register.
15 . The system of claim 14 , wherein the hardcoded register is hardcoded to a zero value.
16 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
detect in a second thread of the plurality of threads a value of a bit indicator, wherein the bit indicator indicates a number of subsequent instructions; and
serially execute the number of subsequent instructions.
17 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
execute an instruction of a second thread of the plurality of threads, in response to completing execution of the plurality of subsequent instructions.
18 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
execute a first instruction of the plurality of subsequent independent instructions at a first clock cycle; and
execute a second instruction of the plurality of subsequent independent instructions at a second clock cycle, wherein the first clock cycle immediately precedes the second clock cycle.
19 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
generate the instruction hint to include a predetermine bit set to a value indicating that a next instruction is an independent instruction.
20 . The system of claim 19 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
detect that the instruction is of a first category; and
set a number of predetermined bits to a value which indicates a number of next independent instructions based on the first category.
21 . The system of claim 20 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
execute the next independent instructions.