Assignment of Assignor's Interest

Recorded: 2024-08-27 Pages: 2

Assignors

KUMAR, KAUSTUBH

Executed: 2024-08-23

MUNNANGI, SIRISHA

Executed: 2024-08-23

BALLIHITALU SATEESHA, SACHIN

Executed: 2024-08-23

NERELAGERE MEGHARAJ, ASHRITH

Executed: 2024-08-23

Assignee

SILICONCH SYSTEMS PVT LTD

#119, 2ND FLOOR, 3RD CROSS, 1ST PHASE, RELIABLE RESIDENCY, HARALUR, BANGALORE, KARNATAKA, 560102, INDIA

Covered Property (1)

Systems and Methods for Real-Number System Verilog Model of Mosfet for Accelerated Mixed-Signal Functional Verification

Application: 18/816,819 →

Publication: US 2025/0371233

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.