Patent Assignment
Reel/Frame 068424/0637
Assignment of Assignor's Interest
Recorded: 2024-08-28
Pages: 7
Assignors
VERMA, PRAVEEN KUMAR
Executed: 2024-08-03
RAWAT, HARSH
Executed: 2024-08-05
KUMAR, PROMOD
Executed: 2024-08-13
Assignee
STMICROELECTRONICS INTERNATIONAL N.V.
CHEMIN DU CHAMP-DES-FILLES 39, PLAN-LES-OUATES, GENEVA, 1228, SWITZERLAND
Covered Property
(1)
Shadow Logic on Output, at Speed Test (Memory Bypass) Architecture for Memories Without Input Data
Application:
63/687,901 →
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 28, 2024
From: FAEHN, ERIC; GOUALOU, LUDOVIC
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 068424/0697 →
Assignment of Assignor's Interest
Nov 7, 2024
From: STMICROELECTRONICS (CROLLES 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 069186/0961 →