IP Library Assignment 068424/0697
Patent Assignment
Reel/Frame 068424/0697

Assignment of Assignor's Interest

Recorded: 2024-08-28 Pages: 5
Assignors
FAEHN, ERIC
Executed: 2024-08-28
GOUALOU, LUDOVIC
Executed: 2024-08-28
Assignee
STMICROELECTRONICS (CROLLES 2) SAS
850 RUE JEAN MONNET, CROLLES, 38920, FRANCE
Covered Property (1)
Shadow Logic on Output, at Speed Test (Memory Bypass) Architecture for Memories Without Input Data
Application: 63/687,901 →
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 28, 2024
From: VERMA, PRAVEEN KUMAR; RAWAT, HARSH; KUMAR, PROMOD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068424/0637 →
Assignment of Assignor's Interest Nov 7, 2024
From: STMICROELECTRONICS (CROLLES 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 069186/0961 →