Providing task-triggered deterministic operational mode for simultaneous multi-threaded superscalar processor

1. A method comprising:

executing a first thread and a second thread, wherein the first thread and the second thread are simultaneously executed on a simultaneous multi-threaded superscalar processor, wherein the first thread is provided with a dual-issue capability such that up to two instructions of the first thread are issued in parallel, and wherein the second thread is provided with a dual-issue capability such that up to two instructions of the second thread are issued in parallel;

retrieving a task identifier of a task from a lookup table, wherein the task is scheduled for execution by a selected thread that is one of the first and second threads, wherein the task identifier is associated with a level of determinism required by the task;

in response to determining that the task requires an increased level of determinism, activating a tag associated with the selected thread;

in response to the tag being read as active, disabling the dual-issue capability of the selected thread; and

re-enabling the disabled dual-issue capability upon the tag being deactivated.

2. The method of claim 1 , further comprising: deactivating the tag upon completion of the task.

3. The method of claim 1 , further comprising: deactivating the tag upon expiration of a duration of time that is defined using an N-bit saturating counter, and wherein the N-bit saturating counter is configured to accumulate a count indicative of how many consecutive instruction issue slots are not filled with an instruction from at least one of the first thread or the second thread.

4. The method of claim 3 , wherein the duration of time expires when the N-bit saturating counter saturates.

5. The method of claim 1 , further comprising: operating a watchdog that is configured to time out after an allowable time so as to prevent a permanent inhibition of the dual-issue capability.

6. The method of claim 1 , further comprising: applying at least one issue policy to instruction queues of the first and second threads.

7. The method of claim 1 , further comprising: deactivating the tag upon expiration of a duration of time of at least N clock cycles, N being a positive integer greater than three.

8. The method of claim 1 , wherein

the first and second threads with enabled dual-issue capability are configured to complete the task within a maximum execution time equal to a predetermined time plus a variation time, and

the increased level of determinism indicates that the task is required to complete within the predetermined time without the variation time.

9. The method of claim 1 , further comprising:

in response to the dual-issue capability being disabled, issuing at least one instruction of the selected thread on a single issue basis.

10. An apparatus comprising:

a processor configured to execute a first thread and a second thread, wherein the first thread is provided with a dual-issue capability such that up to two instructions of the first thread are issued in parallel, and wherein the second thread is provided with a dual-issue capability such that up to two instructions of the second thread are issued in parallel; and

a memory operatively coupled to the processor, the memory configured to store instructions and a task identifier lookup table;

wherein the processor is further configured to:

retrieve a task identifier of a task from the task identifier lookup table, wherein the task is scheduled for execution by a selected thread that is one of the first and second threads, and wherein the task identifier is associated with a level of determinism required by the task;

in response to a determination that the task requires an increased level of determinism, activate a tag associated with the selected thread;

in response to the tag being read as active, disable the dual-issue capability of the selected thread; and

re-enable the disabled dual-issue capability upon the tag being deactivated; and

wherein the processor comprises a simultaneous multi-threaded superscalar processor.

11. The apparatus of claim 10 , wherein the processor is further configured to deactivate the tag upon completion of the task.

12. The apparatus of claim 10 , further comprising an N-bit saturating counter operatively coupled to the processor, wherein the processor is further configured to deactivate the tag upon expiration of a duration of time that is defined using the N-bit saturating counter, and wherein the N-bit saturating counter is configured to accumulate a count indicative of how many consecutive instruction issue slots are not filled with an instruction from at least one of the first thread or the second thread.

13. The apparatus of claim 12 , wherein the duration of time expires when the N-bit saturating counter saturates.

14. The apparatus of claim 10 , wherein the apparatus is provided in the form of one or more integrated circuits.

15. The apparatus of claim 10 , further comprising a watchdog that is configured to time out after an allowable time so as to prevent a permanent inhibition of the dual-issue capability.

16. The apparatus of claim 10 , further comprising first and second issue controllers configured to apply at least one issue policy to instruction queues of the first and second threads.

17. The apparatus of claim 10 , wherein the processor is further configured to deactivate the tag upon expiration of a duration of time of at least N clock cycles, N being a positive integer greater than three.

18. A non-transitory computer readable memory encoded with a computer program comprising computer readable instructions recorded thereon for execution of a method that includes:

executing a first thread and a second thread on a simultaneous multi-threaded superscalar processor, wherein the first thread is provided with a dual-issue capability such that up to two instructions of the first thread are issued in parallel, and wherein the second thread is provided with a dual-issue capability such that up to two instructions of the second thread are issued in parallel;

retrieving a task identifier of a task from a lookup table, wherein the task is scheduled for execution by a selected thread that is one of the first and second threads, wherein the task identifier is associated with a level of determinism required by the task;

in response to determining that the task requires an increased level of determinism, activating a tag associated with the selected thread;

in response to the tag being read as active, temporarily disabling the dual-issue capability of the selected thread; and

re-enabling the disabled dual-issue capability upon the tag being deactivated.

19. The non-transitory computer readable memory of claim 18 , wherein the method further comprises: deactivating the tag upon completion of the task.

20. The non-transitory computer readable memory of claim 18 , wherein the method further comprises: deactivating the tag upon expiration of a duration of time that is defined using an N-bit saturating counter, wherein the N-bit saturating counter is configured to accumulate a count indicative of how many consecutive instruction issue slots are not filled with an instruction from at least one of the first thread or the second thread.

21. The non-transitory computer readable memory of claim 20 , further including instructions wherein the duration of time expires when the N-bit saturating counter saturates.

22. The non-transitory computer readable memory of claim 18 , wherein the method further comprises: deactivating the tag upon expiration of a duration of time of at least N clock cycles, N being a positive integer greater than three.