IP Library Granted Patent US 10,628,061
Granted Patent B2
US 10,628,061 · App. 15/964,178 · Granted Apr 21, 2020

Systems and methods for rebalancing striped information across multiple storage devices

Inventor: Prajakta Chandrakant Zagade (Pune, IN)
Assignee: Veritas Technologies LLC
G06F3/0631G06F3/061G06F3/0653G06F3/0683
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Quick Facts
Patent No.
US 10,628,061
App. No.
15/964,178
Filed
Apr 27, 2018
Granted
Apr 21, 2020
Kind
B2
Art Unit
2136
USPC
711/170
Abstract

The disclosed computer-implemented method for rebalancing striped information across multiple storage devices may include (1) allocating “Y” contiguous storage spaces on “Y” physical devices, (2) dividing, at the computing device, the “Y” continuous storage spaces into “N” subvolumes, (3) allocating the “N” subvolumes to “X” logical stripes, (4) allocating each of the first “Y” logical stripes to a respective physical stripe in each of the “Y” physical stripes, (5) distributing remaining subvolumes to respective logical stripes, and (6) allocating the respective subvolumes across the “Y” physical stripes. Various other methods, systems, and computer-readable media are also disclosed.

Claims (77)

1. A computer-implemented method for rebalancing striped information across multiple storage devices, at least a portion of the method being performed by a computing device comprising at least one processor, the method comprising:

allocating “Y” contiguous physical storage spaces on “Y” physical storage devices in the multiple storage devices to create “Y” physical stripes;

dividing, at the computing device, the “Y” contiguous physical storage spaces into “N” subvolumes;

allocating the “N” subvolumes to “X” logical stripes;

allocating each of the first “Y” logical stripes to a respective physical stripe in each of the “Y” physical stripes;

dividing remaining logical stripes by “Y” to form respective sub-logical stripes; and

allocating the respective sub-logical stripes across the “Y” physical stripes.

2. The computer-implemented method of claim 1 , wherein dividing includes calculating “N” as a least common multiple of {2, 3, . . . X}.

3. The computer-implemented method of claim 1 , further comprising:

tagging at least one logical stripe with a logical stripe identifier.

4. The computer-implemented method of claim 1 , further comprising:

tagging at least one sub-logical stripe with a sub-logical stripe identifier.

5. The computer-implemented method of claim 1 , further comprising:

checking at least one subvolume for overuse; and

moving, when a subvolume is identified as overused, the overused subvolume to a different physical stripe.

6. The computer-implemented method of claim 1 , further comprising:

adding, following allocating the respective sub-logical stripes across the “Y” physical stripes, “P” physical stripes to the multiple storage devices, wherein “P” is an integer;

transferring the Y+1 to Y+P logical stripes and subvolumes therein to the additional “P” physical stripes; and

redistributing subvolumes in Y+P+1 and any higher numbered logical stripes across the Y+P physical stripes.

7. The computer-implemented method of claim 6 , further comprising:

checking at least one subvolume for overuse; and

transferring, when an overused subvolume is detected, the overused subvolume to the additional “P” physical stripes.

8. The computer-implemented method of claim 6 , further comprising:

redistributing subvolumes from the Y+1 logical stripe across the first “Y” physical stripes;

redistributing subvolumes in Y+2 and any higher numbered logical stripes across the first “Y” physical stripes; and

removing the Y+1 physical stripe from the multiple storage devices.

9. The computer-implemented method of claim 8 , further comprising:

checking at least one subvolume for overuse; and

transferring, when an overused subvolume is detected, the overused subvolume to a physical stripe storing a fewest number of subvolumes.

10. The computer-implemented method of claim 1 , further comprising:

redistributing subvolumes from the “Y” logical stripe across the first “Y−1” physical stripes;

redistributing subvolumes in Y+1 and any higher numbered logical stripes across the first “Y−1” physical stripes; and

removing the “Y” physical stripe from the multiple storage devices.

11. The computer-implemented method of claim 10 , further comprising:

checking at least one subvolume for overuse; and

transferring, when an overused subvolume is detected, the overused subvolume to a physical stripe storing a fewest number of subvolumes.

12. The computer-implemented method of claim 10 , further comprising:

adding “P” physical stripes, wherein “P” is an integer;

transferring the Y+1 to Y+P logical stripes and subvolumes therein to the additional “P” physical stripes; and

redistributing subvolumes in Y+P+1 and any higher numbered logical stripes across the Y+P physical stripes.

13. The computer-implemented method of claim 12 , further comprising:

checking at least one subvolume for overuse; and

transferring, when an overused subvolume is detected, the overused subvolume to the additional “P” physical stripes.

14. A system for rebalancing striped information across multiple storage devices, the system comprising:

a first allocating module, stored in memory, that allocates “Y” contiguous physical storage spaces on “Y” physical storage devices in the multiple storage devices to create “Y” physical stripes;

a dividing module, stored in the memory, that divides the “Y” contiguous physical storage spaces into “N” subvolumes;

a second allocating module, stored in the memory, that allocates the “N” subvolumes to “X” logical stripes;

a third allocating module, stored in the memory, that allocates each of the first “Y” logical stripes to a respective physical stripe in each of the “Y” physical stripes;

wherein the dividing module divides remaining logical stripes by “Y” to form respective sub-logical stripes;

an “Nth” allocating module, stored in the memory, that allocates the respective sub-logical stripes across the “Y” physical stripes; and

at least one physical processor that executes the first allocating module, the dividing module, the second allocating module, the third allocating module, and the “Nth” allocating module.

15. The system of claim 14 , further comprising:

a checking module, stored in the memory, that checks at least one subvolume for overuse; and

a moving module, stored in the memory, that moves, when a subvolume is identified as overused, the overused subvolume to a different physical stripe.

16. The system of claim 14 , further comprising:

an adding module, stored in the memory, that adds, following allocating the respective sub-logical stripes across the “Y” physical stripes, “P” physical stripes to the multiple storage devices, wherein “P” is an integer;

a transferring module, stored in the memory, that transfers the Y+1 to Y+P logical stripes and subvolumes therein to the additional “P” physical stripes; and

a redistributing module, stored in the memory, that redistributes subvolumes in Y+P+1 and any higher numbered logical stripes across the Y+P physical stripes.

17. The system of claim 14 , further comprising:

a first redistributing module, stored in the memory, that redistributes subvolumes from the “Y” logical stripe across the first “Y−1” physical stripes;

a second redistributing module, stored in the memory, that redistributes subvolumes in Y+1 and any higher numbered logical stripes across the first “Y−1” physical stripes; and

a removing module, stored in the memory, that removes the “Y” physical stripe from the multiple storage devices.

18. A non-transitory computer-readable medium comprising one or more computer-executable instructions that, when executed by at least one processor of a computing device, cause the computing device to:

allocate “Y” contiguous physical storage spaces on “Y” physical storage devices in multiple storage devices to create “Y” physical stripes;

divide, at the computing device, the “Y” contiguous physical storage spaces into “N” subvolumes;

allocate the “N” subvolumes to “X” logical stripes;

allocate each of the first “Y” logical stripes to a respective physical stripe in each of the “Y” physical stripes;

divide remaining logical stripes by “Y” to form respective sub-logical stripes; and

allocate the respective sub-logical stripes across the “Y” physical stripes.

19. The non-transitory computer-readable medium of claim 18 , further comprising computer-executable instructions that cause the computing device to:

add, following allocating the respective sub-logical stripes across the “Y” physical stripes, “P” physical stripes to the multiple storage devices, wherein “P” is an integer;

transfer the Y+1 to Y+P logical stripes and subvolumes therein to the additional “P” physical stripes; and

redistribute subvolumes in Y+P+1 and any higher numbered logical stripes across the Y+P physical stripes.

20. The non-transitory computer-readable medium of claim 18 , further comprising computer-executable instructions that cause the computing device to:

redistribute subvolumes from the “Y” logical stripe across the first “Y−1” physical stripes;

redistribute subvolumes in Y+1 and any higher logical stripes across the first “Y−1” physical stripes; and

remove the “Y” physical stripe from the multiple storage devices.

Assignments (12)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2026
From: VERITAS TECHNOLOGIES LLC
To: COHESITY, INC.
Reel/Frame 075377/0130 →
AMENDMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Apr 8, 2025
From: VERITAS TECHNOLOGIES LLC; COHESITY, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 070779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2025
From: VERITAS TECHNOLOGIES LLC
To: COHESITY, INC.
Reel/Frame 070335/0013 →
RELEASE OF SECURITY INTEREST Recorded Dec 16, 2024
From: ACQUIOM AGENCY SERVICES LLC, AS COLLATERAL AGENT
To: VERITAS TECHNOLOGIES LLC
Reel/Frame 069697/0238 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2024
From: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: VERITAS TECHNOLOGIES LLC
Reel/Frame 069634/0584 →
SECURITY INTEREST Recorded Dec 9, 2024
From: VERITAS TECHNOLOGIES LLC; COHESITY, INC.
To: JPMORGAN CHASE BANK. N.A.
Reel/Frame 069890/0001 →
ASSIGNMENT OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Nov 25, 2024
From: BANK OF AMERICA, N.A., AS ASSIGNOR
To: ACQUIOM AGENCY SERVICES LLC, AS ASSIGNEE
Reel/Frame 069440/0084 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT R/F 052426/0001 Recorded Nov 30, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: VERITAS TECHNOLOGIES LLC
Reel/Frame 054535/0565 →
SECURITY INTEREST Recorded Aug 20, 2020
From: VERITAS TECHNOLOGIES LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 054370/0134 →
PATENT SECURITY AGREEMENT SUPPLEMENT Recorded Apr 16, 2020
From: VERITAS TECHNOLOGIES, LLC
To: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 052426/0001 →
PATENT SECURITY AGREEMENT SUPPLEMENT Recorded Mar 18, 2020
From: VERITAS TECHNOLOGIES LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 052189/0311 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2018
From: ZAGADE, PRAJAKTA
To: VERITAS TECHNOLOGIES LLC
Reel/Frame 045651/0316 →
Cited By (1)
US 12,379,866