Systems and methods for determining characteristics of semiconductor devices

1. A semiconductor device fabrication structure comprising:

a semiconductor wafer;

a first test structure supported on said semiconductor wafer, said first test structure comprising:

a first oxide layer contacting semiconductor on said semiconductor wafer to form a first interfacial region;

an electrically conducting region exposed to an ambient environment; and

an interconnect surrounded by inter-level dielectric material, said interconnect providing a portion of an electrical path between the electrically conducting region exposed to the ambient environment and the first oxide layer,

wherein the first test structure is configured to receive light from an optical metrology system at said first interfacial region and to produce second harmonic generated light that can be received by said optical metrology system; and

a second test structure on said semiconductor wafer, said second test structure comprising a second oxide layer contacting semiconductor on said semiconductor wafer to form a second interfacial region wherein the second test structure is configured to receive light from the optical metrology system at said second interfacial region and to produce reference second harmonic generated light that can be received by said optical metrology system;

wherein the first and second test structures are not electrically connected to any integrated circuit, and the second oxide layer is not electrically connected to an electrically conducting region exposed to the ambient environment.

2. The semiconductor device fabrication structure of claims 1 wherein the second test structure is included in a space between two integrated circuits.

3. A system for characterizing structures on a sample wafer using second harmonic generation, the system comprising:

an optical source configured to direct a light beam onto said sample wafer;

a positioning system for altering a location the light beam is incident on the sample wafer;

an optical detection system configured to receive second harmonic generated light from said sample wafer; and

electronics configured to;

control the location on said sample wafer said light beam is incident using said positioning system and to receive a signal from said optical detection system based on said second harmonic generated light, and

direct said light beam onto first and second test structures on the sample wafer to generate the second harmonic generated light comprising primary and reference second harmonic generated light;

wherein the first test structure comprises:

a first oxide layer contacting a semiconductor layer on the sample wafer to form a first interfacial region;

an electrically conducting region exposed to an ambient environment; and

an interconnect surrounded by inter-level dielectric material, said interconnect providing a portion of an electrical path between the electrically conducting region exposed to the ambient environment and the first oxide layer, such that said light beam is incident on said first interfacial region which produces the primary second harmonic generated light that is received by said optical detection system;

wherein the second test structure comprises a second oxide layer contacting said semiconductor layer to form a second interfacial region wherein the second interfacial region is configured to receive light from the system at said second interfacial region and to produce the reference second harmonic generated light received by the optical detection system; and

wherein the first and second test structures are not electrically connected to an integrated circuit, and the second oxide layer is not electrically connected to an electrically conducting region exposed to the ambient environment.

4. The system of claim 3 , wherein the system is configured to characterize the sample wafer in-line while the sample wafer is in a fabrication or production line.

5. The system of claim 3 , further comprising a pump source to provide pump radiation to the sample wafer.

6. The system of claim 3 , wherein the electronics is further configured to use the reference second harmonic generated light at least to isolate contribution from process-induced charging or damage to the first interfacial region.

7. A method of determining a change in an electrical property associated with of an interfacial region of a semiconductor device on a sample wafer due to process-induced charging effects, the method comprising:

providing a first test structure on the sample wafer comprising:

a first interfacial region formed on the sample wafer;

a dielectric material over the first interfacial region;

an electrically conducting region on a top surface of the dielectric material, the electrically conducting region being exposed to an ambient environment; and

an interconnect surrounded by the dielectric material, said interconnect providing a portion of an electrical path between the first interfacial region and the electrically conducting region through the dielectric material;

wherein the first test structure is not electrically connected to an integrated circuit, does not include a conductive gate layer, and is not configured

as a functional transistor;

directing radiation from at least one optical source of a metrology system on the first interfacial region;

detecting primary second harmonic generated light from the first interfacial region by an optical detection system of the metrology system;

providing a second test structure comprising a second interfacial region on the sample wafer, the first and second interfacial regions comprising a common layer;

directing radiation from the at least one optical source on the second interfacial region;

detecting reference second harmonic generated light from the second interfacial region by said optical detection system of the metrology system; and

determining the change in the electrical property associated with the first interfacial region based on the primary second harmonic generated light from the first interfacial region and the reference second harmonic generated light from the second interfacial region;

wherein the first and second test structures are not electrically connected to any integrated circuit, and the second interfacial region is not electrically connected to an electrically conducting region.

8. The method of claim 7 , wherein the first interfacial region comprises a junction between a semiconductor layer and a first oxide layer and the second test structure comprises a second oxide layer contacting said semiconductor layer forming the second interfacial region, the first and second oxide layers comprising the same material.

9. The method of Claim 8 , further comprising determining a change in the electrical property associated with the first interfacial region.

10. The method of Claim 9 , further comprising determining a change in the electrical property associated with the first interfacial region of the first test structure based on the second harmonic generated light from the first interfacial region and the second harmonic generated light from the second interfacial region.

11. The method of Claim 8 , wherein determining the change in the electrical property associated with the first interfacial region of the sample wafer is performed in-line while the sample wafer is in a fabrication or production line.

12. The method of claim 7 , wherein directing radiation on the first interfacial region comprises applying pump radiation and probe radiation.