Bitstream controlled reference signal generation for a sigma-delta modulator
View Patent ↗When a reference signal is generated for a digital-to-analog converter in the feedback path of a sigma-delta modulator, the reference signal can contain modulated error signals, for example when the reference generator implements dynamic element matching. By controlling the reference signal generation in dependence on the bitstream output from the sigma-delta modulator, the effects of intermodulation of the reference signal with the bitstream can be reduced.
1. A system for controlling a reference signal generator for a sigma-delta modulator, comprising:
a sigma-delta modulator for providing a bitstream from an input signal, the modulator having a feedback path including a digital-to-analog converter DAC;
a reference signal generator for providing a reference signal for the DAC and configured to implement dynamic element matching that generates residuals, the generator producing a reference signal that includes an error signal pattern that includes the residuals generated by the dynamic element matching; and
a control module for receiving the bitstream and generating a control signal for controlling the error signal pattern in dependence on the bitstream.
2. A system according to claim 1 , wherein the reference signal generator comprises a chopper amplifier, the error signal pattern resulting from chopping in the chopper amplifier.
3. A system according to claim 1 , wherein the bitstream comprises a sequence of first and second values and the dynamic element matching is capable of assuming a plurality of states, the control signal being arranged to assume separate sequences of states for each of the first and second values.
4. A system according to claim 3 , wherein at least one of the separate sequences of states comprises a cyclic pattern.
5. A system according to claim 4 , further comprising means for setting the next state in the sequence of states to have a different value from the preceding state.
6. A system according to claim 5 , wherein the sequence of states comprises first and second states, and the means for setting the next state in the sequence comprises means for switching each state in the sequence between the first and second states.
7. A system according to claim 5 , wherein said setting means comprises a cyclic counter.
8. A system according to claim 5 , wherein said setting means comprises a state machine.
9. A system according to claim 8 , wherein the state machine is selectively enabled by the bitstream.
10. A system according to claim 8 , comprising first and second state machines, each of which is selectively enabled by different values in the bitstream.
11. A system according to claim 6 , wherein the switching means comprises a flip-flop.
12. A system according to claim 11 , comprising first and second flip-flops, each of which is selectively enabled by different values in the bitstream.
13. A system according to claim 1 , wherein the sigma-delta modulator comprises an analog sigma-delta modulator having a programmable gain, wherein the control module includes first and second digital sigma-delta modulators, each of which is selectively enabled by different values in the bitstream.
14. A system according to claim 1 , wherein the digital-to-analog converter comprises a single bit DAC.
15. A system according to claim 1 , wherein the digital-to-analog converter comprises a multi-bit DAC.
16. A method of controlling an error signal pattern in a reference signal generator for a sigma-delta modulator, comprising:
receiving a bitstream from a sigma-delta modulator, the bitstream includes a plurality of values;
generating a control signal for controlling the error signal pattern in dependence on the bitstream, including sequencing through a separate series of states for each of the values in the bitstream; and
selectively enabling a first state machine in response to a first value in the bitstream and selectively enabling a second state machine in response to a second value in the bitstream.
17. A method according to claim 16 , wherein the error signal pattern arises from dynamic element matching in the reference signal generator.
18. A method according to claim 16 , wherein the reference signal generator comprises a chopper amplifier, further comprising selecting an output from a first flip-flop in response to a first value in the bitstream and selecting an output from a second flip-flop in response to a second value in the bitstream, wherein each of the first and second flip-flops provides first and second sequences of values corresponding to the first and second values in the bitstream respectively.
19. A method according to claim 16 , wherein the step of generating the control signal includes selectively enabling a first digital sigma-delta modulator in response to a first value in the bitstream and selectively enabling a second digital sigma-delta modulator in response to a second value in the bitstream.
20. A system comprising:
a sigma-delta modulator for providing a bitstream from an input signal, the modulator having a feedback path including a digital-to-analog converter DAC;
a reference signal generator including a chopper amplifier, the reference signal generator providing a reference signal for the DAC, the reference signal including an error signal pattern resulting from chopping in the chopper amplifier; and
a control module for receiving the bitstream and generating a control signal for controlling the error signal pattern in dependence on the bitstream.
21. A system comprising:
an analog sigma-delta modulator for providing a bitstream from an input signal, the modulator having a programmable gain and having a feedback path including a digital-to-analog converter DAC;
a reference signal generator for providing a reference signal for the DAC, the generator producing a reference signal that includes an error signal pattern; and
a control module for receiving the bitstream and generating a control signal for controlling the error signal pattern in dependence on the bitstream, the control module including first and second digital sigma-delta modulators, each of which is selectively enabled by different values in the bitstream.
22. For use in a system including a sigma-delta modulator and a reference signal generator including a chopper amplifier for producing a reference signal from the sigma-delta modulator, a method of controlling an error signal pattern in the reference signal generator comprising:
receiving a bitstream from a sigma-delta modulator;
generating a control signal for controlling the error signal pattern in dependence on the bitstream;
selecting an output from a first flip-flop in response to a first value in the bitstream, and selecting an output from a second flip-flop in response to a second value in the bitstream, wherein each of the first and second flip-flops provides first and second sequences of values corresponding to the first and second values in the bitstream respectively.
23. A method of controlling an error signal pattern in a reference signal generator for a sigma-delta modulator, comprising:
receiving a bitstream from a sigma-delta modulator;
generating a control signal for controlling the error signal pattern in dependence on the bitstream, including selectively enabling a first digital sigma-delta modulator in response to a first value in the bitstream and selectively enabling a second digital sigma-delta modulator in response to a second value in the bitstream.