HTO offset for long Leffective, better device performance
View Patent ↗Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
1. A memory device comprising:
two or more memory cells on a semiconductor substrate, each memory cell comprising a charge trapping dielectric stack and a poly gate on the semiconductor substrate and two pocket implant regions adjacent and under the charge trapping dielectric stack in the semiconductor substrate;
bit line dielectrics in bit line openings between the memory cells;
bit lines in the semiconductor substrate under the bit line openings; and
spacers adjacent side surfaces of the charge trapping dielectric stack and the poly gate and upper surfaces of the bit lines, wherein a portion of the bit lines touch the spacers.
2. The memory device of claim 1 , wherein the bit lines have a concentration of dopants of about 5E17 atoms/cm 3 or more and about 1E21 atoms/cm 3 or less.
3. The memory device of claim 1 , wherein the bit lines have a depth of about 20 nm or more and about 300 nm or less.
4. The memory device of claim 1 , wherein the pocket implant regions comprise boron and the bit lines comprise arsenic.
5. The memory device of claim 1 , wherein an effective channel length of each memory cell is about 70% or more and about 100% or less of a length of the poly gate.
6. The memory device of claim 1 , wherein a portion of the bit lines are included within a portion of the pocket implant regions.
7. The memory device of claim 1 , wherein the spaces comprise high temperature oxides.
8. A method of making memory cells, comprising sequentially performing the acts of:
providing features and bit line openings therebetween on a semiconductor substrate, the features comprising a charge trapping dielectric stack and a poly gate;
forming pocket implant regions adjacent and under the charge trapping dielectric stack in the semiconductor substrate;
forming spacers adjacent side surfaces of the features and in the bit line openings such that a portion of an upper surface of the semiconductor substrate that is not covered by the spacers is exposed in the bit line opening, the spacers comprising oxides or nitrides; and
forming bit lines under the bit line openings in the semiconductor substrate wherein a portion of the bit lines touch the spacers and a portion of the bit lines are included within a portion of the pocket implant regions.
9. The method of claim 8 , wherein the forming the bit lines comprises implanting one or more dopants at an energy level of about 10 KeV or more and about 100 KeV or less and a dose of about 5E13 atoms/cm 2 or more and about 4E15 atoms/cm 2 or less using the spacers as an implant screen.
10. The method of claim 8 , wherein the forming the spacers comprises a high temperature oxide formation process.
11. The method of claim 8 , wherein the length of the bit line is constrained so that an effective channel length of the memory cell is about 70% or more and about 100% or less of the length of the poly gate.
12. The method of claim 8 further comprising, removing at least a portion of the spacers from the bit line openings and forming bit line dielectrics in the bit line openings.
13. The method of claim 8 further comprising, forming bit line dielectrics in the bit line openings.
14. The method of claim 13 , wherein the bit line dielectrics and the spacers comprise the same material.
15. A method of increasing an effective channel length in memory cells, comprising sequentially performing the acts of:
providing features and bit line openings therebetween on a semiconductor substrate, the features comprising a charge trapping dielectric stack and a poly gate;
forming pocket implant regions adjacent and under the charge trapping dielectric stack in the semiconductor substrate;
forming spacers adjacent side surfaces of the features in the bit line openings such that a portion of an upper surface of the semiconductor substrate that is not covered by the spacers is exposed in the bit line opening, the spacers comprising oxides or nitrides; and
forming bit lines under the bit line openings in the semiconductor substrate by using the spacers as an implant screen to constrain a length of the bit lines wherein a portion of the bit lines touch the spacers and a portion of the bit lines are included within a portion of the pocket implant regions.
16. The method of claim 15 , wherein the forming the spacers comprises a high temperature oxide formation process.
17. The method of claim 15 , wherein the length of the bit line is constrained so that an effective channel length of the memory cell is about 90% or more and about 100% or less of the length of the poly gate.
18. The method of claim 15 , wherein the forming the bit lines comprises implanting one or more dopants at an energy level of about 10 KeV or more and about 100 KeV or less and a dose of about 5E13 atoms/cm 2 or more and about 4E15 atoms/cm 2 or less.
19. The method of claim 15 further comprising, forming bit line dielectrics in the bit line openings.
20. The method of claim 15 further comprising, removing at least a portion of the spacers from the bit line openings and forming bit line dielectrics in the bit line openings.