Chip assembly having via interconnects joined by plating

1. A method of forming a stacked microelectronic assembly comprising the steps of:

(a) juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element, wherein the first semiconductor element has a front surface remote from the major surface, an opening extending between the front and major surfaces thereof at least partly aligned with a surface of a conductive pad exposed at the front surface of the first semiconductor element, wherein the first conductive element is electrically connected to the conductive pad exposed at the front surface of the first semiconductor element through the opening in the first semiconductor element, wherein an interior surface of the opening of the first semiconductor element is lined with a dielectric layer;

(b) forming an opening extending through the conductive pad exposed at the front surface of the second semiconductor element and through the first conductive element; and

(c) forming a second electrically conductive element through the conductive pad exposed at the front surface of the second semiconductor element, the second conductive element extending at least within the opening in the conductive pad exposed at the front surface of the second semiconductor element and through a thickness of the second semiconductor element, the second conductive element electrically contacting the conductive pad exposed at the front surface of the second semiconductor element and the first conductive element.

2. The method of claim 1 , wherein forming an opening includes forming a first opening extending from a major surface of the second semiconductor element towards the front surface thereof, and a second opening extending from the first opening in the second semiconductor element through the conductive pad exposed at the front surface of the second semiconductor element and the first conductive element, wherein where the first and second openings in the second semiconductor element meet, interior surfaces of the first and second openings of the second semiconductor element extend at different angles relative to the major surface of the second semiconductor element.

3. The method of claim 2 , wherein the opening of the first semiconductor element includes a first opening extending from the major surface thereof towards the front surface thereof, and a second opening extending from the first opening to the conductive pad exposed at the front surface of the first semiconductor element, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the first semiconductor element.

4. The method of claim 1 , wherein at least the second semiconductor element has a plurality of active semiconductor devices disposed therein.

5. The method of claim 4 , wherein the first semiconductor element has a plurality of active semiconductor devices disposed therein.

6. The method of claim 1 , wherein the opening in the second semiconductor element extends between the front surface and a major surface of the second semiconductor element and at least a portion of the second conductive element overlies the major surface of the second semiconductor element.

7. The method of claim 6 , further comprising the steps of:

juxtaposing a portion of the second conductive element overlying the major surface of the second semiconductor element with an electrically conductive pad exposed at a front surface of a third semiconductor element;

forming an opening extending through the conductive pad exposed at the front surface of the third semiconductor element and at least exposing the second conductive element; and

forming a third electrically conductive element through the conductive pad exposed at the front surface of the third semiconductor element, the third conductive element extending at least within the opening of the third semiconductor element and through a thickness of the third semiconductor element, the third conductive element electrically contacting the conductive pad exposed at the front surface of the third semiconductor element and the second conductive element.

8. The method of claim 7 , wherein the conductive pad exposed at the front surface of the third semiconductor element overlies the conductive pad exposed at the front surface of the first semiconductor element.

9. The method of claim 7 , wherein the conductive pad exposed at the front surface of the third semiconductor element at least partly overlies the major surface of the second semiconductor element.

10. The method of claim 1 , wherein the first semiconductor element has a plurality of active semiconductor devices therein, and the major surface of the first semiconductor element is a front surface thereof, wherein the first conductive element is at least one of a conductive pad or a conductive element electrically connected with a conductive pad.

11. The method of claim 1 , wherein the first semiconductor element has a plurality of active semiconductor devices therein.

12. The method of claim 1 , wherein the entirety of the conductive pad exposed at the front surface of the second semiconductor element overlies the major surface of the first semiconductor element.

13. The method of claim 1 , further comprising forming at least one dielectric layer overlying at least one of the major surface of the first semiconductor element or the front surface of the second semiconductor element prior to step (a).

14. The method of claim 13 , wherein the at least one dielectric layer is an adhesive.

15. The method of claim 13 , wherein the second conductive element fully fills the opening of the second semiconductor element with metal through the first conductive element to a major surface of the second semiconductor element, wherein the metal extends beyond the first conductive element into the at least one dielectric layer.

16. The method of claim 13 , wherein the second conductive element fills the opening of the second semiconductor element with metal through the first conductive element to a height above the first conductive element, the second conductive element including a layer of metal extending beyond the height along an interior surface of the opening of the second semiconductor element, the layer partially occupying a space within the opening of the second semiconductor element above the height, wherein the metal extends beyond the first conductive element into the at least one dielectric layer.

17. The method of claim 1 , wherein the first conductive element includes a pad overlying the major surface of the first semiconductor element.

18. The method of claim 1 , wherein at least a portion of the second conductive element conforms to a contour of an interior surface of the opening in the second semiconductor element.

19. The method of claim 1 , wherein at least a portion of the second conductive element does not conform to a contour of an interior surface of the opening in the second semiconductor element.

20. The method of claim 1 , wherein the second conductive element fully fills the opening of the second semiconductor element with metal through the first conductive element to a major surface of the second semiconductor element.

21. The method of claim 1 , wherein the second conductive element fills the opening of the second semiconductor element with metal through the first conductive element to a height above the first conductive element, the second conductive element including a layer of metal extending beyond the height along an interior surface of the opening, the layer partially occupying a space within the opening above the height.

22. A method of forming a stacked microelectronic assembly comprising the steps of:

(a) juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element, wherein the first semiconductor element has a front surface remote from the major surface, an opening extending between the front and major surfaces thereof at least partly aligned with a surface of a conductive pad exposed at the front surface of the first semiconductor element, wherein the first conductive element is electrically connected to the conductive pad exposed at the front surface of the first semiconductor element through the opening in the first semiconductor element, wherein an interior surface of the opening of the first semiconductor element is lined with a dielectric layer, wherein the second semiconductor element includes a first opening extending from a rear surface of the second semiconductor element towards the front surface thereof, the first opening of the second semiconductor element being at least partially aligned with the conductive pad exposed at the front surface of the second semiconductor element;

(b) forming a second opening in the second semiconductor element extending from the first opening of the second semiconductor element through the conductive pad exposed at the front surface of the second semiconductor element and through the first conductive element; and

(c) forming a second electrically conductive element extending through the first and second openings of the second semiconductor element, through the conductive pad exposed at the front surface of the second semiconductor element and the first conductive element, the second conductive element electrically connecting the conductive pad exposed at the front surface of the second semiconductor element and the first conductive element.

23. The method of claim 22 , wherein the opening of the first semiconductor element includes a first opening extending from the major surface thereof towards the front surface thereof, and a second opening extending from the first opening to the conductive pad exposed at the front surface of the first semiconductor element, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the first semiconductor element.

24. An assembly, comprising:

a first semiconductor element having a first conductive element exposed at a major surface thereof, wherein the first semiconductor element has a front surface remote from the major surface, an opening extending between the front and major surfaces thereof at least partly aligned with a surface of a conductive pad exposed at the front surface of the first semiconductor element, wherein the first conductive element is electrically connected to the conductive pad exposed at the front surface of the first semiconductor element through the opening in the first semiconductor element, wherein an interior surface of the opening of the first semiconductor element is lined with a dielectric layer;

a second semiconductor element having a front surface juxtaposed with the major surface of the first semiconductor element, a plurality of active semiconductor devices therein, and a conductive pad exposed at the front surface thereof, the conductive pad exposed at the front surface of the second semiconductor element at least partly overlying the first conductive element, the second semiconductor element including an opening extending from a major surface thereof through the conductive pad exposed at the front surface of the second semiconductor element and the first conductive element; and

a first metal element extending within the opening of the second semiconductor element, through a thickness of the second semiconductor element, and through the conductive pad exposed at the front surface of the second semiconductor element, the first metal element electrically interconnecting the conductive pad exposed at the front surface of the second semiconductor element with the first conductive element.

25. The assembly of claim 24 , wherein the opening of the second semiconductor element includes a first opening extending from the major surface of the second semiconductor element towards the front surface thereof, and a second opening extending from the first opening of the second semiconductor element through the conductive pad exposed at the front surface of the second semiconductor element, wherein where the first and second openings of the second semiconductor element meet, interior surfaces of the first and second openings of the second semiconductor element extend at different angles relative to the major surface of the second semiconductor element.

26. The assembly of claim 25 , wherein the opening of the first semiconductor element includes a first opening extending from the major surface thereof towards the front surface thereof, and a second opening extending from the first opening to the conductive pad exposed at the front surface of the first semiconductor element, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the first semiconductor element.

27. The assembly of claim 24 , wherein the first metal element includes at least a portion overlying the major surface of the second semiconductor element.

28. The assembly of claim 24 , further comprising:

a third semiconductor element having a front surface juxtaposed with the major surface of the second semiconductor element, a plurality of active semiconductor devices therein, and a conductive pad exposed at the front surface thereof, the conductive pad exposed at the front surface of the third semiconductor element at least partly overlying the major surface of the second semiconductor element, the third semiconductor element including an opening extending from a major surface thereof through the conductive pad exposed at the front surface thereof and the first metal element; and

a second metal element extending within the opening of the third semiconductor element and electrically interconnecting the conductive pad exposed at the front surface of the third semiconductor element with the first metal element.

29. The assembly of claim 28 , wherein the conductive pad exposed at the front surface of the third semiconductor element at least partly overlies the first conductive element.

30. The assembly of claim 24 , wherein the first metal element includes a portion at least partially filling the opening of the second semiconductor element.

31. The assembly of claim 24 , wherein at least one dielectric layer overlies at least one of the major surface of the first semiconductor element and the front surface of the second semiconductor element.

32. The assembly of claim 31 , wherein the at least one dielectric layer is an adhesive.

33. The assembly of claim 31 , wherein the first metal element fully fills the opening of the second semiconductor element with metal through the first conductive element to the major surface of the second semiconductor element, wherein the metal extends beyond the first conductive element into the at least one dielectric layer.

34. The assembly of claim 31 , wherein the first metal element fills the opening of the second semiconductor element with metal through the first conductive element to a height above the first conductive element, the first metal element including a layer of metal extending beyond the height along an interior surface of the opening of the second semiconductor element, the layer partially occupying a space within the opening of the second semiconductor element above the height, wherein the metal extends beyond the first conductive element into the at least one dielectric layer.

35. The assembly of claim 24 , wherein the first conductive element includes a pad overlying the major surface of the first semiconductor element.

36. The assembly of claim 24 , wherein the entirety of the conductive pad exposed at the front surface of the second semiconductor element overlies the major surface of the first semiconductor element.

37. The assembly of claim 24 , wherein at least a portion of the first metal element conforms to a contour of a surface of the opening of the second semiconductor element.

38. The assembly of claim 24 , wherein at least a portion of the first metal element does not conform to a contour of a surface of the opening of the second semiconductor element.

39. The assembly of claim 24 , wherein the first semiconductor element includes a plurality of active semiconductor devices.

40. The assembly of claim 24 , wherein the first metal element fully fills the opening of the second semiconductor element with metal through the first conductive element to the major surface of the second semiconductor element.

41. The assembly of claim 24 , wherein the first metal element fills the opening of the second semiconductor element with metal through the first conductive element to a height above the first conductive element, the first metal element including a layer of metal extending beyond the height along an interior surface of the opening of the second semiconductor element, the layer partially occupying a space within the opening of the second semiconductor element above the height.

42. A system comprising an assembly according to claim 24 and one or more other electronic components electrically connected to the assembly.

43. A system as claimed in claim 42 further comprising a housing, the assembly and the other electronic components being mounted to the housing.