IP Library Granted Patent US 6,915,083
Granted Patent B1
US 6,915,083 · App. 09/212,203 · Granted Jul 5, 2005

Signal receiver having wide band amplification capability

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Quick Facts
Patent No.
US 6,915,083
App. No.
09/212,203
Granted
Jul 5, 2005
Kind
B1
Abstract

An Improved Signal Receiver Having Wide Band Amplification Capability is disclosed. Also disclosed is a receiver that is able to receive and reliably amplify infrared and/or other wireless signals having frequency bandwidths in excess of 40 MHz. The receiver of the present invention reduces the signal-to-noise ratio of the received signal to ⅕th of the prior systems. The preferred receiver eliminates both the shunting resistor and the feedback resistor on the input end by amplifying the signal in current form. Furthermore, the receiver includes transconductance amplification means for amplifying the current signal without the need for Cascode stages. Finally, the receiver includes staged amplification to amplify the current signal in stages prior to converting the signal into a voltage output.

Claims (24)

1. An improved infrared transceiver system comprising:

a first sensor for detecting infrared signals incident thereon and converting said signals to an electrical current signal;

a gain controller for amplifying said current signals;

a voltage converter for converting said current signals into voltage signals; and

a staged current amplifier in circuit between said gain controller and said voltage converter, said staged current amplifier comprised of at least two amplification stages, each of said stages amplifying said current signals, wherein said gain controller comprises a current mirror in operative connection with said staged current amplifier and further wherein said staged current amplifier comprises:

a first transistor, said first transistor comprising a first drain and a first gate;

a second transistor, said second transistor comprising a second source and a second drain, said second source being in circuit with said first drain;

a third transistor, said third transistor comprising a third gate and a third source, said third gate being in circuit with said second drain; and

a fourth transistor, said fourth transistor comprising a fourth drain and a fourth gate, said fourth drain in circuit with said fourth gate and said first gate.

2. The system of claim 1 , wherein said current mirror is in circuit with said second drain and said third gate.

3. The system of claim 1 , further comprising an output terminal, said output terminal being in circuit with said third source and said fourth drain.

4. The system of claim 3 , wherein each of said transistors comprises a bias voltage, and wherein said bias voltage is dynamically adjustable in order to operate each of said transistors in a weak inversion range.

5. An improved wireless signal receiver system comprising:

a first sensor for detecting wireless signals incident thereon and converting said signals to an electrical current signal;

a gain controller for amplifying said current signals; and

a voltage converter for converting said current signals into voltage signals;

wherein said gain controller further comprises a staged current amplifier operating in the weak inversion range, and a current mirror in operative connection with said current amplifier; and wherein said current amplifier comprises:

a first transistor, said first transistor comprising a first drain and a first gate;

a second transistor, said second transistor comprising a second source and a second drain, said second source being in circuit with said first drain;

a third transistor, said third transistor comprising a third gate and a third source, said third gate being in circuit with said second drain; and

a fourth transistor, said fourth transistor comprising a fourth drain and a fourth gate, said fourth drain in circuit with said fourth gate and said first gate.

6. The system of claim 5 , wherein said current mirror is in circuit with said second drain and said third gate.

7. The system of claim 5 , further comprising an output terminal, said output terminal being in circuit with said third source and said fourth drain.

8. The system of claim 7 , wherein each of said transistors comprises a bias, voltage, and wherein said bias voltage is dynamically adjustable in order to operate each of said transistors in a weak inversion range.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2015
From: IXYS CH GMBH
To: IXYS INTL LIMITED
Reel/Frame 035665/0810 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2010
From: ZILOG, INC.
To: IXYS CH GMBH
Reel/Frame 024964/0132 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2001
From: CALIBRE, INC.
To: ZILOG, INC.
Reel/Frame 011743/0946 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 1998
From: HAMILTON, T. ALLAN; GRACE, ALAN
To: CALIBRE, INC.
Reel/Frame 009653/0688 →