IP Library Granted Patent US 6,910,193
Granted Patent B1
US 6,910,193 · App. 09/273,820 · Granted Jun 21, 2005

System and method for executing tests on an integrated circuit design

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Quick Facts
Patent No.
US 6,910,193
App. No.
09/273,820
Granted
Jun 21, 2005
Kind
B1
Abstract

The present invention is generally directed to a system and method for performing evaluation tests on a circuit design. Specifically, the present invention is directed to a system and method that controllably executes test routines on a netlist file. Broadly, the system of the present invention is a software package that is configured to execute a wide variety of tests, checks, or evaluations on a circuit design, as defined by a netlist file. An inventive aspect lies in the controllable execution of the various tests, checks, and evaluations, whereby certain tests may be omitted. In accordance with this novel aspect of the invention, the program may look to one or more files that contain a listing of tests that would otherwise be performed by the program, but which the program omits if listed in any of the one or more exclusion files. Preferably, the system employs two such exclusion files: one which is located in a “local” directory (i.e., the same location from which the program is being launched), and a “global” exclusion file, which is located in a predetermined, or specified, location.

Claims (28)

1. A method for performing design tests on a circuit design comprising the steps of:

(a) evaluating a first file that identifies at least one test;

(b) evaluating a second file that identifies at least one test;

(c) executing a plurality of predefined tests, excluding all tests that are identified in the first file and all tests identified in the second file;

(d) creating a list of executed tests; and

(e) adding to the list of executed tests every executed test in response to the execution of each test.

2. The method as defined in claim 1 , further including the step of comparing the list of executed tests, after all tests have been executed, to the tests listed in both the first and second files.

3. The method as defined in claim 2 , further including the step of reporting an error if any test listed in the list of executed tests is also listed in either the first or second file.

4. A method for performing design tests on a circuit design comprising the steps of:

(a) evaluating a first file that identifies at least one test;

(b) evaluating a second file that identifies at least one test;

(c) evaluating a third file that lists a plurality of tests to be permissibly excluded;

(c) executing a plurality of predefined tests, excluding tests that are identified in the first file and tests identified in the second file; and

(d) comparing the at least one test in the first file and the at least one test in the second file with the plurality of tests in the third file, to ensure that all tests listed in the first and second files are also listed in the third file.

5. A computer readable storage medium containing program code for performing design tests on a circuit design comprising:

a first code segment configured to evaluate a first file that identifies at least one test;

a second code segment configured to evaluate a second file that identifies at least one test; and

a third code segment configured to execute a plurality of predefined tests, excluding tests that are identified in the first file and tests identified in the second file.

6. The system as defined in claim 5 , further including a fourth code segment configured to create a list of each test that is executed by the third code segment.

7. The system as defined in claim 6 , further including a fifth code segment configured to compare the tests listed in the list of each test against the tests identified in the first file and the tests identified in the second file.

8. The system as defined in claim 7 , further including sixth code segment configured to generate an error message if any of the tests listed in the list of each test is listed in either the first file or the second file.

9. A system for performing design tests on a circuit design comprising:

a first file stored at a first location, the first file identifying at least one test;

a second file stored at a second location, the second file identifying at least one test;

means for executing a plurality of predefined tests, excluding tests that are identified in the first file and tests identified the second file, wherein the means for executing the plurality of tests is configured to execute all tests identified in the first file and all tests identified in the second file.

10. The system as defined in claim 9 , further including means for creating a list of each test that is executed by the means for executing the plurality of tests.

11. The system as defined in claim 10 , further including means for comparing the tests listed in the list of each test against the tests identified in the first file and the tests identified in the second file.

12. The system as defined in claim 11 , further including means for generating an error message if any of the tests listed in the list of each test is listed in either the first file or the second file.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2011
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.; HEWLETT-PACKARD COMPANY
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026198/0139 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2005
From: HEWLETT-PACKARD COMPANY
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 016033/0859 →
CLARIFICATION TO PATENT AND PATENT APPLICATION ASSIGNMENT Recorded Mar 31, 2005
From: HEWLETT-PACKARD COMPANY; AGILENT TECHNOLOGIES INC.; HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT-PACKARD COMPANY; HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.; AGILENT TECHNOLOGIES, INC.
Reel/Frame 015980/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2005
From: AGILENT TECHNOLOGIES, INC.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 015980/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2000
From: HEWLETT-PACKARD COMPANY
To: AGILENT TECHNOLOGIES INC.; HEWLETT-PACKARD COMPANY
Reel/Frame 011089/0573 →
MERGER Recorded Apr 24, 2000
From: HEWLETT-PACKARD COMPANY
To: HEWLETT-PACKARD COMPANY
Reel/Frame 010759/0049 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 1999
From: MCBRIDE, JOHN C.
To: HEWLETT-PACKARD COMPANY
Reel/Frame 010067/0383 →