Patent Assignment
Reel/Frame 026198/0139
Assignment of Assignor's Interest
Recorded: 2011-04-26
Received: 2011-04-26
Pages: 43
Assignors
HEWLETT-PACKARD COMPANY
Executed: 2010-10-19
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Executed: 2010-10-19
Assignee
SAMSUNG ELECTRONICS CO., LTD.
416 MAETAN-DONG, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, KRX, KOREA, REPUBLIC OF
Covered Properties
(100)
Creating High Voltage Fets with Low Voltage Process
Application:
12/350,102 →
Multilayer Film with Stack of Nanometer-Scale Thicknesses
Application:
12/104,252 →
Fabrication of Aligned Nanowire Lattices
Application:
11/842,818 →
Field-Effect-Transistor Multiplexing/Demultiplexing Architectures
Application:
11/765,374 →
Methods of Forming Through-Substrate Interconnects
Application:
11/654,338 →
Method and System for Offset Estimation and Alignment
Application:
11/584,074 →
Superlattice for Fabricating Nanowires
Application:
11/582,002 →
Deformation-Based Contact Lithography Systems, Apparatus and Methods
Application:
11/548,975 →
Repair Techniques for Memory with Multiple Redundancy
Application:
11/507,272 →
Fabrication of Nano-Object Array
Application:
11/457,776 →
Package Having Bond-Sealed Underbump
Application:
11/447,764 →
Vacuum Device Having Non-Evaporable Getter Component with Increased Exposed Surface Area
Application:
11/387,222 →
Placement of Absorbing Material in a Semiconductor Device
Application:
11/276,875 →
Fluidic Mems Device
Application:
11/350,662 →
Wafer Packaging and Singulation Method
Application:
11/340,321 →
Metallic Quantum Dots Fabricated by a Superlattice Structure
Application:
11/271,354 →
On-Chip Variable Oscillator Method and Apparatus
Application:
11/266,863 →
Mechanism for Resolving Ambiguous Invalidates in a Computer System
Application:
11/258,586 →
Contact Lithography Apparatus, System and Method
Application:
11/203,551 →
Clock Pulse Width Control Circuit
Application:
11/179,400 →
Creating High Voltage Fets with Low Voltage Process
Application:
11/176,033 →
Use of Expanding Material Oxides for Nano-Fabrication
Application:
11/174,798 →
Fabrication of Aligned Nanowire Lattices
Application:
11/169,470 →
Data Storage Device Including Nanotube Electron Sources
Application:
11/136,882 →
Array of Nanoscopic Mosfet Transistors and Fabrication Methods
Application:
11/126,710 →
Cooling Devices That Use Nanowires
Application:
11/126,430 →
Laser-Assisted Deposition
Application:
11/105,262 →
Light Modulator Device
Application:
11/101,820 →
Photonic Crystals with Nanowire-Based Fabrication
Application:
11/096,669 →
Mems Device and Method of Forming Mems Device
Application:
11/092,410 →
Nano-Vcsel Device and Fabrication Thereof Using Nano-Colonnades
Application:
11/084,886 →
Fabrication and Assembly Structures and Methods for Memory Devices
Application:
11/080,284 →
Photonic Device
Application:
11/080,113 →
Method of Forming Multilayer Film
Application:
11/068,363 →
Patterning Nanoline Arrays with Spatially Varying Pitch
Application:
11/061,226 →
Method of Utilizing a Contact Printning Stamp
Application:
11/046,107 →
Assembly with a Ring and Bonding Pads Formed of a Same Material on a Substrate
Application:
11/038,374 →
Wafer Packaging and Singulation Method
Application:
11/011,640 →
Placement of Absorbing Material in a Semiconductor Device
Application:
11/008,542 →
Mirror Device for Projection System Having Plurality of Tiltable Mirrors Tilted
Application:
10/995,690 →
Micro-Displays and Their Manufacture
Application:
10/977,278 →
Lithographic Mask Alignment
Application:
10/960,731 →
E-Field Polarized Materials
Application:
10/945,756 →
Emitter and Method of Making
Application:
10/935,795 →
Defect Management Enabled Pirm and Method
Application:
10/931,842 →
Imprint Lithography Apparatus and Method Employing an Effective Pressure
Application:
10/931,672 →
Logical Arrangement of Memory Arrays
Application:
10/896,163 →
Etching with Electrostatically Attracted Ions
Application:
10/895,733 →
Embossed Mask Lithography
Application:
10/885,842 →
Methods and Systems for Loading Data from Memory
Application:
10/861,710 →
Package Having Bond-Sealed Underbump
Application:
10/854,110 →
Method of Making a Tunneling Emitter
Application:
10/848,695 →
Field-Effect-Transistor Multiplexing/Demultiplexing Architectures and Methods of Forming the Same
Application:
10/835,659 →
Etching
Application:
10/832,640 →
Method for Patterning an Organic Light Emitting Diode Device
Application:
10/830,508 →
Wheatstone Bridge Scheme for Sensor
Application:
10/828,334 →
Integrated Focusing Emitter
Application:
10/825,754 →
Fabrication and Use of Superlattice
Application:
10/817,729 →
Method of Creating a Patterned Monolayer on a Surface
Application:
10/817,135 →
Structure Formed with Template Having Nanoscale Features
Application:
10/807,873 →
Using Local Storage to Handle Multiple Outstanding Requests in a Sci System
Application:
10/803,289 →
Micro Mirror Device with Adjacently Suspended Spring and Method for the Same
Application:
10/793,977 →
Wafer Packaging and Singulation Method
Application:
10/776,084 →
Address Structure and Methods for Multiple Arrays of Data Storage Memory
Application:
10/777,000 →
Imprint Stamp
Application:
10/766,710 →
Emitter with Filled Zeolite Emission Layer
Application:
10/758,801 →
Silicon-Based Dielectric Tunneling Emitter
Application:
10/755,890 →
Fabricationof Nano-Object Array
Application:
10/744,516 →
Power Control Unit That Provides One of a Plurality of Voltages on a Common Power Rail
Application:
10/734,855 →
Method and Apparatus for Measurement Using Piezoelectric Sensor
Application:
10/735,197 →
Method and Apparatus for Measuring Jitter
Application:
10/732,035 →
Back Pressure Test Fixture to Allow Probing of Integrated Circuit Package Signals
Application:
10/725,715 →
System and a Method for Fluid Filling Wafer Level Packages
Application:
10/700,713 →
Large Line Conductive Pads for Interconnection of Stackable Circuitry
Application:
10/696,992 →
Method of Designing Custom Circuit Device Using Scheduling Clock Cycles
Application:
10/699,241 →
Fabrication and Assembly Structures and Methods for Memory Devices
Application:
10/697,457 →
Data Storage Devices with Wafer Alignment Compensation
Application:
10/695,566 →
Memory Controller Driver Circuitry Having a Multiplexing Stage to Provide Data to at Least N-1 of N Data Propagation Circuits, and Having Output Merging Circuitry to Alternately Couple the N Data Propagation Circuits to a Data Pad to Generate Either a 1X or Mx Stream of Data
Application:
10/695,881 →
Device Having a Getter Structure and a Photomask
Application:
10/689,819 →
Method of Manufacturing an Emitter
Application:
10/688,731 →
Tunneling Emitters
Application:
10/686,965 →
A Method of Forming Electrical Interconnects Having Electromigration-Inhibiting Segments to a Critical Length
Application:
10/681,843 →
Fabrication of Nanowires
Application:
10/683,527 →
A Pressure Sensor and Method of Making the Same Having Membranes Forming a Capacitor
Application:
10/666,609 →
Transistor with Group Iii/Vi Emitter
Application:
10/666,434 →
Bistable Molecular Mechanical Devices with a Middle Rotating Segment Activated by an Electric Field for Electronic Switching, Gating, and Memory Applications
Application:
10/660,277 →
Integrated Circuit
Application:
10/655,640 →
Clock Skew Measurement Circuit on a Microprocessor Die
Application:
10/655,321 →
Power Estimation Based on Power Characterizations
Application:
10/653,650 →
System and Method for Providing Predicate Data to Multiple Pipeline Stages
Application:
10/648,960 →
Data Signal Reception Latch Control Using Clock Aligned Relative to Strobe Signal
Application:
10/650,071 →
Testing a Processor Using a Random Code Generator
Application:
10/647,296 →
System and Method for Determining Unmatched Design Elements in a Computer-Automated Design
Application:
10/647,608 →
Systems and Methods Utilizing Fast Analysis Information During Detailed Analysis of a Circuit Design
Application:
10/647,687 →
System and Method for Iteratively Traversing a Hierarchical Circuit Design
Application:
10/647,688 →
Method and System to Temporarily Modify an Output Waveform
Application:
10/646,935 →
Imprinting Nanoscale Patterns for Catalysis and Fuel Cells
Application:
10/642,371 →
Method and System for Sizing a Load Plate
Application:
10/639,853 →
System and Method for Measuring Fault Coverage in an Integrated Circuit
Application:
10/627,564 →
Enhanced Electron Field Emitter Spindt Tip and Method for Fabricating Enhanced Spindt Tips
Application:
10/622,909 →