Method and apparatus for measuring jitter

1. A method of measuring jitter, comprising:

generating a jitter pulse having a width corresponding to an amount of jitter; and

providing the jitter pulse to a first latch of a plurality (M) of latches serially coupled to successively trim the pulse as it propagates through the serially coupled latches, wherein each latch, l i , provides an output b i indicative of receipt of an edge of the jitter pulse.

2. The method of claim 1 wherein each selected latch, l i sets its output, b i in response to one edge of any received pulse, wherein the selected latch trims its received pulse having pulse width r i by a pre-determined amount d i , wherein the selected latch provides a corresponding output pulse of width o i =r i −d i when r i >d i and no output pulse when r i ≦d i .

3. The method of claim 2 wherein the d i are substantially identical such that d i =d j ∀i, jε{1, 2, . . . M}.

4. The method of claim 1 wherein the successive outputs form a thermometer coded value, b M . . . b 1 , representative of the amount of jitter.

5. The method of claim 1 further comprising:

sensing multiple latch outputs to determine the amount of jitter.

6. The method of claim 5 wherein sensing multiple latch outputs further comprises proceeding from the Mth latch toward the first latch to determine the amount of jitter.

7. The method of claim 5 wherein sensing multiple latch outputs further comprises sensing a k th latch to determine if the amount of jitter exceeds a pre-determined threshold, wherein 1≦k≦M.

8. The method of claim 1 wherein generating the jitter pulse and providing the jitter pulse are performed by integrated circuitry residing on an integrated circuit die.

9. A jitter measurement apparatus comprising:

a phase/frequency detector apparatus providing a jitter pulse having a pulse width corresponding to an amount of jitter in a clock signal; and

a plurality (M) of serially coupled latches at least one receiving the jitter pulse, wherein each latch l i propagates a trimmed pulse having a shorter pulse width than its received pulse, wherein each latch l i provides an output b i indicative of receipt of an edge of any pulse received by that latch.

10. The apparatus of claim 9 wherein each selected latch, l i sets its output, b i in response to one edge of any received pulse, wherein the selected latch trims its received pulse having pulse width r i by a pre-determined amount d i , wherein the selected latch provides a corresponding output pulse of width o i =r i −d i when r i >d i and no output pulse when r i ≦d i .

11. The apparatus of claim 10 wherein the d i are substantially identical such that d i =d j ∀i, jε{1, 2, . . . M}.

12. The apparatus of claim 9 wherein the successive b i outputs form a thermometer-coded value, b M . . . b 1 , representative of the amount of jitter.

13. The apparatus of claim 9 wherein the phase/frequency detector apparatus and the plurality of latches reside on a same integrated circuit die.

14. The apparatus of claim 9 further comprising:

a phase locked loop for generating a clock from a reference clock CLK 1 , wherein a feedback loop of the phase locked loop provides a clock signals CLK 2 , wherein the phase/frequency detector apparatus is coupled to provide a signal corresponding to an edge alignment difference between CLK 1 and CLK 2 .

15. The apparatus of claim 9 wherein the phase/frequency detector apparatus comprises:

a phase/frequency detector providing first and second pulse trains, wherein a relative difference between the first and second pulse trains indicates which of a first clock, CLK 1 and a second clock CLK 2 leads the other; and

a pulse difference generator providing the jitter pulse, wherein the width of the jitter pulse corresponds to a magnitude of the difference in alignment between CLK 1 and CLK 2 .

16. The apparatus of claim 9 wherein each latch l i further comprises:

a plurality of inverters coupled to provide the trimmed pulse from the received pulse; and

a flip-flop having a clock input coupled to receive the trimmed pulse, wherein an output of the flip-flop corresponds to output b i .

17. The apparatus of claim 16 wherein the plurality of inverters comprises first and second serially-coupled inverters, wherein the first and second inverters are sized to skew a leading edge of the received pulse more than a falling edge of the received pulse.

18. The apparatus of claim 9 wherein the phase/frequency detector apparatus and the plurality of serially-coupled latches reside on an integrated circuit die.

19. The apparatus of claim 17 wherein the integrated circuit die is a complementary metal oxide semiconductor (CMOS) integrated circuit die.