Clock pulse width control circuit
View Patent ↗In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.
1. A clock pulse width control circuit, comprising:
a plurality of timer circuits to generate a plurality of delayed pulse signals from an input clock signal wherein at least one timer circuit comprises:
a first circuit to generate an output signal corresponding to a delay in a rising edge of the clock signal, wherein the first circuit comprises:
an asymmetric unbalanced inverter to invert the rising edge of the control signal;
at least one capacitive element coupled to an output of the inverter; and
a Schmitt trigger coupled to the capacitive element; and
a second circuit to generate an output signal corresponding to a delay in a falling edge of the clock signal;
a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal; and
a selection circuit to select one of the output signals.
2. The clock pulse width control circuit of claim 1 , wherein the second circuit comprises at least one discharge transistor coupled to the capacitive element and the Schmitt trigger.
3. The clock pulse width control circuit of claim 1 , further comprising a bypass AND gate to generate an output signal from the clock signal.
4. The clock pulse width control circuit of claim 1 , wherein the output signal generated by the AND gates comprises:
a rising edge delayed by a first time period from the rising edge of the input clock signal;
a falling edge delayed by a second time period from the rising edge of the input clock signal.
5. The clock pulse width control circuit of claim 1 , wherein the selection circuit comprises at least one multiplexer.
6. A clock pulse width control circuit, comprising:
a timer circuit to generate a delayed pulse signal from an input clock signal, wherein the timer circuit comprises:
a first circuit to generate an output signal corresponding to a delay in a rising edge of the clock signal, wherein the first circuit comprises:
an asymmetric unbalanced inverter to invert the rising edge of the control signal;
at least one capacitive element coupled to an output of the inverter; and
a Schmitt trigger coupled to the capacitive element; and
a second circuit to generate an output signal corresponding to a delay in a falling edge of the clock signal,
wherein the delayed pulse signal comprises:
a falling edge delayed by a first time period in response to a rising edge in the clock signal; and
a rising edge delayed by a second time period, different from the first time period, in response to a falling edge in the clock signal; and
an AND gate to generate an output signal from the delayed pulse signal and the input clock signal.
7. The clock pulse width control circuit of claim 6 , wherein the second circuit comprises at least one discharge transistor coupled to the capacitive element and the Schmitt trigger.
8. The clock pulse width control circuit of claim 6 , further comprising a bypass AND gate to generate an output signal from the clock signal.
9. The clock pulse width control circuit of claim 6 , wherein the output signal generated by the AND gate comprises:
a rising edge delayed by a first time period from the rising edge of the input clock signal;
a falling edge delayed by a second time period from the rising edge of the input clock signal.
10. A clock pulse width control circuit, comprising:
means for generating a plurality of delayed pulse signals from an input clock signal, wherein the means for generating a plurality of delayed pulse signals from an input clock signal comprises:
a first circuit to generate an output signal corresponding to a delay in a rising edge of the clock signal, wherein the first circuit comprises:
an asymmetric unbalanced inverter to invert the rising edge of the control signal;
at least one capacitive element coupled to an output of the inverter; and
a Schmitt trifler coupled to the capacitive element; and
a second circuit to generate an output signal corresponding to a delay in a falling edge of the clock signal;
means for generating a corresponding plurality of output signals from the delayed pulse signals and the input clock signal; and
means for selecting one of the output signals.
11. The clock pulse width control circuit of claim 10 , wherein the second circuit comprises at least one discharge transistor coupled to the capacitive element and the Schmitt trigger.
12. The clock pulse width control circuit of claim 10 , further comprising a bypass AND gate to generate an output signal from the clock signal.
13. The clock pulse width control circuit of claim 10 , wherein the output signals comprise:
a rising edge delayed by a first time period from the rising edge of the input clock signal;
a falling edge delayed by a second time period from the rising edge of the input clock signal.
14. The clock pulse width control circuit of claim 10 , wherein the means for selecting one of the output signals comprises at least one multiplexer.