Creating high voltage FETs with low voltage process

1. An integrated circuit having a set of first-conductivity-wells and second-conductivity-wells formed on a substrate, comprising:

a self-aligned LV first-conductivity FET transistor having first-conductivity+ active areas and a set of channel stops formed in a first second-conductivity-well; and

a non self-aligned HV-second-conductivity FET transistor formed in a second first-conductivity-well wherein a drain region is defined by a degraded lightly doped second-conductivity-drift regions formed by a chained implant used to form the channel stops and a second-conductivity+ active area defined by a first spacer spanning the drain region and partially the gate region of the HV-second-conductivity FET.

2. The integrated circuit of claim 1 , further comprising:

a self-aligned LV second-conductivity FET transistor having second-conductivity+ active areas formed in a first first-conductivity-well.

3. The integrated circuit of claim 1 , further comprising:

a non self-aligned HV-first-conductivity FET transistor formed in a second second-conductivity-well wherein a drain region is defined by a first-conductivity-drift region formed during the creation of the set of first-conductivity-wells and a first-conductivity+ active area defined by a spacer spanning the drain region and partially a gate region, and wherein the gate region is formed during the creation of the first second-conductivity-well and wherein the first-conductivity+ active areas of the LV first-conductivity FET and the HV-first-conductivity FET are formed at the same time.

4. The integrated circuit of claim 2 wherein the LV first-conductivity FET and LV second-conductivity FET transistors have a drain to source breakdown of less then about 7V.

5. The integrated circuit of claim 3 wherein the HV-second-conductivity FET and the HV-first-conductivity FET transistors have a drain to source breakdown of greater than about 20V.

6. A high voltage first-conductivity type field effect transistor (HV-first-conductivity FET), comprising:

a second-conductivity-well;

a field oxide formed over the second-conductivity-well defining an active area;

a first-conductivity-well formed in at least a portion of the active area, wherein the first-conductivity-well is formed of chained implants to create a degraded lightly-doped first conductivity drift region to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET,

a gate oxide formed over the second-conductivity-well and a portion of the first-conductivity-well in the active area; and

a plurality of spacers formed on opposing sides of the gate oxide, a spacer defining an opening over the first-conductivity-well, the opening having a first-conductivity+ implant in the first-conductivity-well.

7. The HV-first-conductivity FET of claim 6 , further comprising:

a second first-conductivity-well formed in at least a portion of the active area, wherein the second first-conductivity-well is formed of chained implants to create a degraded lightly-doped first conductivity drift region to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET;

a second spacer defining a second opening over the second first-conductivity-well, the second opening having a second first-conductivity+ implant in the second first-conductivity-well; and

wherein the gate oxide is further formed over a portion of the second first-conductivity-well.

8. The HV-first-conductivity FET of claim 6 , further comprising:

a second first-conductivity+ implant in the active area of the second-conductivity-well, and wherein the gate region is formed over a portion of the second first-conductivity+ implant;

a second spacer adjacent to the second first-conductivity+ implant; and

a low density diffusion implant under the gate oxide and adjacent to the second first-conductivity+ implant.

9. A high voltage first conductivity-type field effect transistor (HV-first-conductivity FET), comprising:

a second-conductivity-well;

a field oxide formed over the second-conductivity-well defining an active area;

a channel stop region formed in at least a portion of the active area, wherein the channel stop region is formed chained implants to create a degraded lightly-doped first conductivity drift region to have the capability to operate as first-conductivity-drift portions of the HV-first-conductivity FET,

a gate oxide formed over the second-conductivity-well and a portion of the channel stop region in the active area; and

a plurality of spacers formed on opposing sides of the gate oxide, a spacer defining an opening over the channel stop region, the opening having a first-conductivity+ implant in the channel stop region.

10. The HV-first-conductivity FET of claim 9 , further comprising:

a second channel stop region formed in at least a portion of the active area, wherein the second channel stop region is formed of chained implants to create a degraded lightly-doped first conductivity drift region to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET;

a second spacer defining a second opening over the second channel stop region, the second opening having a second first-conductivity+ implant in the second channel stop region; and

wherein the gate oxide is further formed over a portion of the second channel stop region.

11. The HV-first-conductivity FET of claim 9 , further comprising:

a second first-conductivity+ implant in the active area of the second-conductivity-well, and wherein the gate region is formed over a portion of the second first-conductivity+ implant; and

a second spacer adjacent to the second first-conductivity+ implant.

12. An integrated circuit (IC), comprising:

a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET), including:

a second-conductivity-well;

a field oxide formed over the second-conductivity-well defining an active area;

a first-conductivity-well formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET,

a gate oxide formed over the second-conductivity-well and a portion of the first-conductivity-well in the active area; and

a plurality of spacers formed on opposing sides of the gate oxide, a spacer defining an opening over the first-conductivity-well, the opening having a first-conductivity+ implant in the first-conductivity-well; and

a high voltage second-type field effect transistor (HV-second-conductivity FET), including:

a first-conductivity-well;

a field oxide formed over the first-conductivity-well defining an active area;

a channel stop region formed in at least a portion of the active area, wherein the channel stop region is formed of chained implants to create a degraded lightly-doped first conductivity drift region to have the capability to operate as second-conductivity-drift portions of the HV-second-conductivity FET,

a gate oxide formed over the first-conductivity-well and a portion of the channel stop region in the active area; and

a plurality of spacers formed on opposing sides of the gate oxide, a spacer defining an opening over the channel stop region, the opening having a second-conductivity+ implant in the channel stop region.

13. The IC of claim 12 wherein the HV-first-conductivity FET, further includes:

a second first-conductivity-well formed in at least a portion of the active area, wherein the second first-conductivity-well is formed to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET;

a second spacer defining a second opening over the second first-conductivity-well, the second opening having a second first-conductivity+ implant in the second first-conductivity-well; and

wherein the gate oxide is further formed over a portion of the second first-conductivity-well.

14. The IC of claim 12 wherein the HV-first-conductivity FET, further includes:

a second first-conductivity+ implant in the active area of the second-conductivity-well, and wherein the gate region is formed over a portion of the second first-conductivity+ implant;

a second spacer adjacent to the second first-conductivity+ implant; and

a low density diffusion implant under the gate oxide and adjacent to the second first-conductivity+ implant.

15. The IC of claim 12 wherein the HV-second-conductivity FET, further includes:

a second channel stop region formed in at least a portion of the active area, wherein the second channel stop region is formed of chained implants to create a degraded lightly-doped first conductivity drift region to have the capability to operate as a second-conductivity-drift portion of the HV-second-conductivity FET;

a second spacer defining a second opening over the second channel stop region, the second opening having a second second-conductivity+ implant in the second channel stop region; and

wherein the gate oxide is further formed over a portion of the second channel stop region.

16. The IC of claim 12 wherein the HV-second-conductivity FET, further includes:

a second second-conductivity+ implant in the active area of the first-conductivity-well, and wherein the gate region is formed over a portion of the second second-conductivity+ implant; and

a second spacer adjacent to the second second-conductivity+ implant.

17. The IC of claim 12 , further comprising:

a set of self aligned transistors of at least one of group consisting of LV first-conductivity FET and LV second-conductivity FET transistors, wherein the LV first-conductivity FET and LV second-conductivity FET transistors have a drain to source breakdown of less then about 7V.