IP Library Granted Patent US 7,026,189
Granted Patent B2
US 7,026,189 · App. 10/776,084 · Granted Apr 11, 2006

Wafer packaging and singulation method

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Quick Facts
Patent No.
US 7,026,189
App. No.
10/776,084
Granted
Apr 11, 2006
Kind
B2
Abstract

A method for packaging and singulating a wafer having a plurality of micro devices includes providing a multi-lid substrate having a trench having intersection portions and non-intersection portions formed on a first side of the multi-lid substrate. The multi-lid substrate is coupled to the wafer such that the intersection portions of the trench pattern extend adjacent to at least three micro devices. Portions of the multi-lid substrate between a second side of the multi-lid substrate and the trench pattern are removed while the multi-lid substrate is coupled to the wafer.

Claims (46)

1. A method for packaging and singulating a micro device wafer having a plurality of micro devices, the method comprising:

providing a multi-lid substrate with a trench pattern on a first side of the multi-lid substrate, the trench pattern having intersection portions and non-intersection portions;

coupling the multi-lid substrate to the micro device wafer such that the intersection portions of the trench pattern extend adjacent to at least two micro devices;

providing a protective material between a floor of the trench pattern and an opposite portion of the micro device wafer; and

subsequently removing portions of the multi-lid substrate between a second side of the multi-lid substrate and the trench pattern while the multi-lid substrate is coupled to the micro device wafer.

2. The method of claim 1 , wherein the trench pattern is configured such that only a single non-intersection portion extends between consecutive micro devices of the micro device wafer when the multi-lid substrate is coupled to the micro device wafer.

3. The method of claim 1 , wherein each micro device includes a main portion and a contact point projecting from the main portion, wherein the non-intersection portion of the trench pattern has a width forming an opening adjacent to at least one contact point of at least one device when the multi-lid substrate is coupled to the micro device wafer.

4. The device of claim 3 , wherein the opening is adjacent a first contact point of a first micro device and a second contact point of a consecutive second micro device.

5. The method of claim 3 , wherein each micro device has a plurality of contact points projecting from the main portion and wherein the opening is adjacent the plurality of contact points.

6. The method of claim 1 , wherein each micro device has a main portion, a first contact point on a first side of the main portion and a second contact point on a second side of the main portion and wherein the trench pattern is configured to form openings adjacent the first contact point and the second contact point when the multi-lid substrate is coupled to the micro device wafer.

7. The method of claim 1 , wherein the trench pattern extends opposite a passageway portion of the micro device wafer when the multi-lid substrate is coupled to the micro device wafer and wherein the micro device wafer is separated into dies along separation lines within the passageway portion.

8. The method of claim 1 , wherein the multi-lid substrate includes a glass material.

9. The method of claim 1 , wherein the trench pattern is formed by cutting into the first side of the multi-lid substrate.

10. The method of claim 9 , wherein the trench pattern is formed by a process selected from a group including:

photolithography, sand drilling, laser cutting, use of a water jet, molding and material deposition.

11. The method of claim 9 , wherein the portions are removed by cutting into the second side of the multi-lid substrate.

12. The method of claim 11 , wherein the portions are removed by sawing into the second side of the multi-lid substrate.

13. The method of claim 1 , wherein the portions are removed by cutting into the second side of the multi-lid substrate.

14. The method of claim 1 , wherein each micro device includes a main portion and a contact point projecting from the main portion and wherein the step of coupling the multi-lid substrate to the micro device wafer includes forming a seal between the multi-lid substrate and the micro device wafer and about each main portion between each main portion and each contact point.

15. The method of claim 14 , wherein the step of forming a seal includes locating a bond ring about each main portion between each main portion and each contact point.

16. The method of claim 15 , wherein the step of locating the bond ring includes coupling the bond ring to the multi-lid substrate prior to coupling the multi-lid substrate to the micro device wafer.

17. The method of claim 15 , wherein the step of locating the bond ring includes coupling the bond ring to the micro device wafer prior to coupling the multi-lid substrate to the micro device wafer.

18. The method of claim 1 , wherein at least one of the micro devices includes a micro machine.

19. The method of claim 18 , wherein the plurality of micro devices includes at least one display micro machine.

20. The method of claim 1 , wherein the multi-lid substrate is at least semi-transparent.

21. The method of claim 1 , wherein the non-intersection portions of the trench pattern have a width of between about 50 and 2000 micrometers and a depth of between about 50 and 1000 micrometers.

22. The method of claim 1 , wherein the multi-lid substrate is spaced from the micro device.

23. The method of claim 1 , wherein the multi-lid substrate is formed from a non-silicon material.

24. The method of claim 1 including separating the micro device wafer into dies.

25. The method of claim 1 including coating the floor portion of the trench pattern with the protective material.

26. The method of claim 1 including applying the protective material to the opposite portion of the micro device wafer.

27. The method of claim 26 including removing the protective material from the opposite portion of the micro device wafer.

28. A method for packaging and singulating a micro device wafer having a plurality of micro devices, the method comprising:

providing a multi-lid substrate having a trench pattern on a first side of the multi-lid substrate, the trench pattern having intersection portions and non-intersection portions;

coupling the multi-lid substrate to the micro device wafer, wherein the trench pattern is configured such that only a single non-intersection portion of the trench pattern extends between consecutive micro devices of the micro device wafer when the multi-lid substrate is coupled to the micro device wafer;

providincg a protective material between a floor of the trench pattern and an opposite portion of the micro device wafer; and

subsequently removing portions of the multi-lid substrate between a second side of the multi-lid substrate and the trench pattern while the multi-lid substrate is coupled to the micro device wafer.

29. The method of claim 1 , wherein each micro device includes a main portion and a contact point projecting from the main portion, wherein the step of coupling the multi-lid substrate to the micro device wafer includes forming a seal between the multi-lid substrate and the micro device wafer and about each main portion between each main portion and each contact point and wherein the protective material is provided between adjacent seals.

30. The method of claim 1 , wherein each micro device includes a main portion and a contract point projecting from the main portion and wherein the protective material overlies the contact point and does not overlie the main portion.

31. The method of claim 1 , wherein the protective material comprises polyvinyl acetate.

32. The method of claim 28 including coating the floor portion of the trench pattern with the protective material.

33. The method of claim 28 including applying the protective material to the opposite portion of the micro device wafer.

34. The method of claim 28 including removing the protective material from the opposite portion of the micro device wafer.

35. The method of claim 28 , wherein each micro device includes a main portion and a contact point projecting from the main portion, wherein the step of coupling the multi-lid substrate to the micro device wafer includes forming a seal between the multi-lid substrate and the micro device wafer and about each main portion between each main portion and each contact point and wherein the protective material is provided between adjacent seals.

36. The method of claim 28 , wherein each micro device includes a main portion and a contract point projecting from the main portion and wherein the protective material overlies the contact point and does not overlie the main portion.

37. The method of claim 28 , wherein the protective material comprises polyvinyl acetate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2011
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.; HEWLETT-PACKARD COMPANY
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026198/0139 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 1ST AND 3RD INVENTORS AND THEIR DOC. DATES. PREVIOUSLY RECORDED ON REEL 014989 FRAME 0407. Recorded Sep 9, 2004
From: CHEN, CHIEN-HUA; JOHN, BRADLEY C; LANIG, CHARLOTTE R; WORKMAN, MELISSA A
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 015115/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2004
From: CHEN, CHIEN-HUA; JOHN, BRADLEY C.; LANIG, CHARLOTTE R.; WORKMAN, MELISSA A.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 014989/0407 →