Field-effect-transistor multiplexing/demultiplexing architectures
View Patent ↗This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.
1. A system comprising:
an array of conductive structures having a pitch from about one to about ninety nanometers; and
a multiplexing/demultiplexing architecture having address lines and address field-effect transistors (FETs), the address lines in electrical communication with the conductive structures through the address FETs.
2. The system of claim 1 , wherin the conductive structures comprise highly conductive and semi-conductive regions.
3. The system of claim 2 , further comprises an array of dielectric structures in physical proximity to the highly conductive regions and the semi-conductive regions, wherein the dielectric structures in physical proximity to the semi-conductive regions are capable of acting as gates for the address FETs.
4. The system of claim 1 , further comprises an array of dielectric structures, the dielectric structures having thin regions and thick regions, the thin regions capable of acting as gates for the address FETs.
5. A system comprising:
an array of conductive structures:
an array of dielectric structures having thick and thin regions in proximity with the conductive structures: and
a multiplexing/demultiplexing architecture having address lines in proximity with the dielectric structures, the address lines and the thick or thin regions forming field-effect transistors (FETs) enabling electrical communication between the address lines and the conductive structures.
6. The system of claim 5 , wherein the array of conductive structures has a pitch of less than or about ninety nanometers.
7. The system of claim 5 , wherein the conductive structures each comprise highly conductive and semi-conductive regions.
8. The system of claim 7 , wherein the thick regions of the dielectric structures are in physical proximity with the semi-conductive regions and form the FETs.
9. The system of claim 5 , wherein the thick and thin regions of the dielectric structures have substantially a same width as the conductive structures with which each is in proximity.