Logical arrangement of memory arrays
View Patent ↗An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least one address line coupled to the controller wherein a number of connections from the controller to the at least one power line, the at least one sense line and the at least one address line is minimized.
1. A logical arrangement of memory arrays comprising:
a plurality of memory arrays deposed in a row-column configuration;
a controller coupled to the plurality of memory arrays;
at least one power line wherein the at least one power line includes a column power line, and a row power line, at least one sense line and at least one address line coupled to the controller; and
at least one column address bus wherein each column power line is connected to at least one of the plurality of memory arrays such that each column power line connects to one memory array in each row of the row-column configuration wherein no two memory arrays connected to a column power line share a column address bus.
2. The arrangement of claim 1 wherein the at least one power line includes a column address line and a row address line.
3. The arrangement of claim 1 wherein each memory array includes a memory element and at least one diode.
4. The arrangement of claim 1 wherein the at least one sense line is associated with a row in the row-column configuration.
5. A memory system comprising:
a plurality of stacked memory layers wherein at least one of the plurality of memory layers includes a controller wherein each of the plurality of memory layers includes
a plurality of memory arrays deposed in a row-column configuration coupled to the controller;
at least one power line including a column power line and a row power line, at least one sense line and at least one address line coupled to the controller; and
at least one column address bus wherein each column power line is connected to at least one of the plurality of memory arrays such that each column power-line connects to one memory array in each row of the row-column configuration wherein no two memory arrays connected to a column power line share a column address bus.
6. The memory system of claim 5 wherein the at least one address line includes a column address line and a row address line.
7. The memory system of claim 5 wherein each memory array includes a memory element and at least one diode.
8. The memory system of claim 5 wherein the at least one sense line is associated with a row in the row-column configuration.
9. The memory system of claim 5 wherein the number of memory arrays equals a number of columns in the row-column configuration multiplied by the number of rows in the row-column configuration multiplied by the number of superarrays.
10. The memory system of claim 9 wherein the total number of connections in the memory system comprises the following relationship:
2
K
Q
+
Q
(
N
+
2
M
)
wherein K is the number of arrays in a superarray, Q is the number of rows, N is the number of superarrays and M is a number of row or column address lines per memory array.
11. A logical arrangement of memory arrays comprising:
a plurality of memory arrays deposed in a row-column configuration wherein each memory array includes a memory element and at least one diode;
a controller coupled to the plurality of memory arrays;
at least one power line coupled to the controller wherein the at least one power line includes a column power line and a row power line;
at least one sense line coupled to the controller wherein the at least one sense line is associated with a row in the row-column configuration;
at least one address line coupled to the controller wherein the at least one address line includes a column address line and a row address line; and
at least one column address bus wherein each column power line is connected to at least one of the plurality of memory arrays such that each column power line connects to one memory array in each row of the row-column configuration wherein no two memory arrays connected to a column power line share a column address bus.
12. A memory system comprising:
a plurality of stacked memory layers wherein at least one of the plurality of memory layers includes a controller wherein each of the plurality of memory layers includes
a plurality of memory arrays deposed in a row-column configuration wherein each memory array includes a memory element and at least one diode;
a controller coupled to the plurality of memory arrays;
at least one power line coupled to the controller wherein the at least one power line includes a column power line and a row power line;
at least one sense line coupled to the controller wherein the at least one sense line is associated with a row in the row-column configuration;
at least one address line coupled to the controller wherein the at least one address line includes a column address line and a row address line; and
at least one column address bus wherein each column power line is connected to at least one of the plurality of memory arrays such that each column power line connects to one memory array in each row of the row-column configuration wherein no two memory arrays connected to a column power line share a column address bus.
13. The memory system of claim 12 wherein the number of memory arrays equals a number of columns in the row-column configuration multiplied by the number of rows in the row-column configuration multiplied by the number of superarrays.
14. The memory system of claim 13 wherein the total number of connections in the memory system comprises the following relationship:
2
K
Q
+
Q
(
N
+
2
M
)
wherein K is the number of arrays in a superarray, Q is the number of rows, N is the number of superarrays and M is a number of row or column address lines per memory array.