Method for forming variable length instructions in a processing system
View Patent ↗Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode portion. The opcode portion specifies an operation to be performed, the number of parameters in the instruction, and definitive characteristics of the parameters. The parameters may represent data which is compressible, thereby enabling the size of parameters in an instruction to be reduced.
1. A method of forming instructions for execution in a processing system, said method comprising:
providing an opcode portion determining at least one instruction to be performed by the processing system; and
providing a first parameter byte including a first set of data value bits, and a first expansion bit indicative of whether the processing system expands the first set of data value bits or reads any additional parameter bytes including additional sets of data value bits.
2. The method of claim 1 , wherein said first byte further has a sign bit indicative of whether the first set of data value bits represents a positive number or a negative number.
3. The method of claim 1 , further comprising
providing a second parameter byte including a second set of data value bits, and a second expansion bit indicative of whether the processing system expands the second set of data value bits or reads any additional parameter bytes including additional sets of data value bits.
4. The method of claim 3 , wherein said first byte further has a sign bit indicative of whether the first set of data value bits and the second set of data value bits collectively represent a positive number or a negative number.
5. The method of claim 3 , further comprising
providing a third parameter byte including a third set of data value bits, and a third expansion bit indicative of whether the processing system expands the third set of data value bits or reads any additional parameter bytes including additional sets of data value bits.
6. The method of claim 5 , wherein said first byte further has a sign bit indicative of whether the first set of data value bits, the second set of data value bits and the third set of data value bits collectively represent a positive number or a negative number.