Patent Assignment
Reel/Frame 027265/0798
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2011-11-22
Received: 2011-11-22
Pages: 99
Assignor
NXP B.V.
Executed: 2011-09-26
Assignee
CALLAHAN CELLULAR L.L.C.
2711 CENTERVILLE ROAD, SUITE 400, WILMINGTON, DE, 19808, UNITED STATES
Covered Applications
(100)
MLPPP OCCUPANCY BASED ROUND ROBIN
App. No. 12/915,790
→
IN-SYSTEM METHOD FOR MEASUREMENT OF CLOCK RECOVERY AND OSCILLATOR DRIFT
App. No. 12/900,760
→
LOW VOLTAGE, HIGH-SPEED OUTPUT-STAGE FOR LASER OR MODULATOR DRIVING
App. No. 11/577,182
→
DIVERSITY ANTENNA ASSEMBLY FOR WIRELESS COMMUNICATION EQUIPMENT
App. No. 11/915,812
→
DATA PROCESSING SYSTEM AND METHOD FOR INTERCONNECT ARBITRATION
App. No. 11/630,599
→
DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY
App. No. 12/340,547
→
ELECTRONIC STREAM PROCESSING CIRCUIT WITH LOCALLY CONTROLLED PARAMETER UPDATES, AND METHOD OF DESIGNING SUCH A CIRCUIT
App. No. 12/256,334
→
RADIO FREQUENCY PWM & PPM MODULATOR
App. No. 12/293,812
→
ELECTRONIC CIRCUIT WITH LOW NOISE DELAY CIRCUIT
App. No. 12/158,315
→
INTEGRATED CIRCUIT WITH INTERNAL COMMUNICATION NETWORK
App. No. 11/915,285
→
INTEGRATING ANALOG TO DIGITAL CONVERTER
App. No. 12/092,859
→
RF SELECTION SWITCH FOR MULTIPLE ANTENNA INPUT
App. No. 11/574,234
→
ULTRA LOW POWER LVDS DRIVER WITH BUILT IN IMPEDANCE TERMINATION TO SUPPLY AND GROUND RAILS
App. No. 11/587,104
→
FLAT TUNER MODULE WITH A STANDARD CONNECTOR
App. No. 11/578,880
→
CALIBRATING AMPLITUDE AND PHASE IMBALANCE AND DC OFFSET OF AN ANALOG I/Q MODULATOR IN A HIGH-FREQUENCY TRANSMITTER
App. No. 11/722,084
→
DATA COMMUNICATION IN NETWORKS COMPRISING A PLURALITY OF NETWORK NODES AND AT LEAST ONE STAR NODE
App. No. 11/741,399
→
WLAN SCHEDULER
App. No. 10/555,554
→
TUNABLE CASCODE LNA WITH FLAT GAIN RESPONSE OVER A WIDE FREQUENCY RANGE
App. No. 11/575,065
→
RECEIVER FRONT-END SENSITIVITY BOOSTER
App. No. 10/552,831
→
APPARATUS COMPRISING A CHARGE PUMP AND LCD DRIVER COMPRISING SUCH AN APPARATUS
App. No. 11/572,916
→
LAND PRE-PIT SIGNAL PROCESSING METHOD AND RELATED APPARATUS
App. No. 11/630,093
→
WIRELESS DEVICE WITH DYNAMIC FRAGMENTATION THRESHOLD ADJUSTMENT
App. No. 10/569,128
→
METHOD AND APPARATUS FOR WRITING DATA TO AN OPTICAL DISC
App. No. 11/629,770
→
INTERFACE DEVICE FOR DEBUGGING AND/OR TRACING A COMPUTER SYSTEM COMPRISING ONE OR MULTIPLE MASTERS AND ONE OR MULTIPLE SLAVES WORKING TOGETHER
App. No. 11/629,897
→
EXTENDED CONVOLUTIONAL CODES
App. No. 11/628,124
→
DATA PROCESSING SYSTEM WITH TRACE CO-PROCESSOR
App. No. 11/596,326
→
IMAGE PROCESSING METHOD AND APPARATUS ADJUSTING IMAGE DATA IN ACCORDANCE WITH IMAGE DATA SUB-PIXELS
App. No. 11/596,332
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PIPELINED ASYNCHRONOUS INSTRUCTION PROCESSOR HAVING TWO WRITE PIPELINE STAGES WITH CONTROL OF WRITE ORDERING FROM STAGES TO MAINTAIN SEQUENTIAL PROGRAM ORDERING
App. No. 11/568,197
→
METHOD OF DOWN-SAMPLING DATA VALUES
App. No. 11/587,028
→
COMBINING SIGNAL-INTERFERENCE-RATIO (SIR) ESTIMATES FOR IMPROVED SIR ESTIMATION
App. No. 11/547,739
→
VIDEO PROCESSING CIRCUIT AND METHOD OF VIDEO PROCESSING
App. No. 10/591,390
→
ELECTRONIC STREAM PROCESSING CIRCUIT WITH LOCALLY CONTROLLED PARAMETER UPDATES, AND METHOD OF DESIGNING SUCH A CIRCUIT
App. No. 10/597,992
→
REMOTE CONTROL SYSTEM AND RELATED METHOD AND APPARATUS
App. No. 10/589,111
→
INTEGRATED CIRCUIT DEVICE WITH A ROM MATRIX
App. No. 10/587,646
→
METHOD AND APPARATUS FOR OVER CLOCKING IN A DIGITAL PROCESSING SYSTEM
App. No. 10/587,607
→
HIGH SPEED COMPARATOR
App. No. 10/578,052
→
DELAY FAULT TEST CIRCUITRY AND RELATED METHOD
App. No. 10/584,705
→
UNIVERSAL DEROTATOR FOR UMTS MODES
App. No. 10/584,043
→
METHOD AND ARRANGEMENT FOR INTERFERENCE COMPENSATION IN A VOLTAGE-CONTROLLED FREQUENCY GENERATOR
App. No. 10/596,454
→
ADAPTIVE FILTER
App. No. 10/572,474
→
INITIAL SYNCHRONIZATION FOR RECEIVERS
App. No. 10/572,473
→
PARALLEL PROCESSING ARRAY
App. No. 10/568,013
→
MEMORY ORGANIZATION ALLOWING SINGLE CYCLE POINTER ADDRESSING WHERE THE ADDRESS OF THE POINTER IS ALSO CONTAINED IN ONE OF THE MEMORY LOCATIONS
App. No. 10/566,514
→
HIGH FREQUENCY COMPONENT
App. No. 10/565,934
→
ANTENNA SWITCH WITH ADAPTIVE FILTER
App. No. 10/565,150
→
METHOD AND APPARATUS FOR COARSE AND FINE FREQUENCY AND TIMING SYNCHRONISATION
App. No. 10/563,926
→
COMMUNICATION DEVICE AND AN ANTENNA THEREFOR
App. No. 10/563,649
→
FRAME FORMAT DECODER AND TRAINING SEQUENCE GENERATOR FOR WIRELESS LAN NETWORKS
App. No. 10/561,856
→
METHOD FOR CANCELLING A NARROW-BAND INTERFERENCE SIGNAL
App. No. 10/561,459
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DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY
App. No. 10/560,450
→
CONTROL SYSTEM FOR A VOLTAGE CONVERTER
App. No. 10/559,911
→
FREQUENCY MULTIPLEXED ARCHITECTURE
App. No. 10/558,726
→
LOW PASS FILTER AND ELECTRONIC DEVICE
App. No. 10/558,718
→
METHOD AND DEVICE FOR ESTIMATING IQ IMBALANCE
App. No. 10/557,660
→
CIRCUIT FOR GENERATING A HIGH-FREQUENCY OSCILLATION IN A SPECIFIED FREQUENCY BAND
App. No. 10/537,855
→
CARRIER RECOVERY BASED DEMODULATION
App. No. 10/555,269
→
IMPEDANCE MATCHING CIRCUIT FOR A MULTI-BAND RADIO FREQUENCY DEVICE
App. No. 11/243,683
→
LOW LATENCY RADIO BASEDBAND INTERFACE PROTOCOL
App. No. 10/526,591
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UP AND DOWN SAMPLE RATE CONVERTER
App. No. 10/550,875
→
ELECTRONICALLY CONTROLLABLE RF SWITCH
App. No. 10/550,346
→
TRACK AND HOLD CIRCUIT
App. No. 10/550,343
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MULTILAYER STACK WITH COMPENSATED RESONANT CIRCUIT
App. No. 10/549,883
→
Microstrip Filter of Short Length
App. No. 10/549,350
→
UNIVERSAL MEMORY DEVICE HAVING A PROFILE STORAGE UNIT
App. No. 10/549,367
→
DATA PROCESSING SYSTEM WITH PREFETCHING MEANS
App. No. 10/547,594
→
CONTROL METHOD AND DEVICE FOR A DISPLAY DEVICE
App. No. 10/545,866
→
ARRANGEMENT OF A CHEMICAL-MECHANICAL POLISHING TOOL AND METHOD OF CHEMICAL-MECHANICAL POLISHING USING SUCH A CHEMICAL-MECHANICAL POLISHING TOOL
App. No. 11/197,755
→
METHOD OF PRODUCING SEMICONDUCTOR ELEMENTS USING A TEST STRUCTURE
App. No. 10/539,103
→
PHASE CORRECTED MILLER COMPENSATION OF CHOPPER AND NESTED CHOPPER AMPLIFIERS
App. No. 10/538,562
→
TUNABLE TRACKING FILTER
App. No. 10/538,372
→
TESTABLE CASCODE CIRCUIT AND METHOD FOR TESTING THE SAME USING A GROUP OF SWITCHING ELEMENTS
App. No. 10/509,863
→
SLIDING BIAS CIRCUIT FOR ENABLING DYNAMIC CONTROL OF QUIESCENT CURRENT IN A LINEAR POWER AMPLIFIER
App. No. 10/538,348
→
SELF ADAPTABLE BIAS CIRCUIT FOR ENABLING DYNAMIC CONTROL OF QUIESCENT CURRENT IN A LINEAR POWER AMPLIFIER
App. No. 10/538,347
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METHOD AND ARRANGEMENT FOR BRINGING TOGETHER DATA ON PARALLEL DATA PATHS
App. No. 10/505,028
→
DECOUPLING MODULE FOR DECOUPLING HIGH-FREQUENCY SIGNALS FROM A VOLTAGE SUPPLY LINE
App. No. 10/536,236
→
SDRAM ADDRESS MAPPING OPTIMIZED FOR TWO-DIMENSIONAL ACCESS
App. No. 10/535,783
→
TRAVELLING-WAVE AMPLIFIER
App. No. 10/535,056
→
FREQUENCY-INDEPENDENT VOLTAGE DIVIDER
App. No. 10/531,603
→
TRANSMIT AND RECEIVE ANTENNA SWITCH
App. No. 10/531,033
→
SYSTEM AND METHOD FOR MAINTAINING COHERENCY AND TRACKING VALIDITY IN A CHACHE HIEARCHY
App. No. 10/530,143
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DEVICE WRITING TO A PLURALITY OF ROWS IN A MEMORY MATRIX SIMULTANEOUSLY
App. No. 10/525,662
→
OPERATIONAL AMPLIFIER
App. No. 10/524,570
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VARIABLE GAIN AMPLIFIER WITH IMPROVED CONTROL CHARACTERISTICS LINEARITY
App. No. 10/524,182
→
COUPLER, INTEGRATED ELECTRONIC COMPONENT AND ELECTRONIC DEVICE
App. No. 10/498,757
→
INTEGRATED CIRCUIT WITH TEST CIRCUIT
App. No. 10/506,234
→
DUAL MODE TUNING ARRANGEMENT
App. No. 10/523,382
→
SETTING THE SLICE LEVEL IN A BINARY SIGNAL
App. No. 10/522,470
→
OPTICAL RECEIVER CIRCUIT
App. No. 10/520,314
→
ERASABLE AND PROGRAMMABLE NON-VOLATILE CELL
App. No. 10/520,340
→
AUTOMATIC FREQUENCY CONTROL RECEIVER
App. No. 10/519,605
→
TELEVISION RECEIVER WITH ISOLATED INPUTS
App. No. 10/519,062
→
PULSE WIDTH MODULATION SIGNAL GENERATOR
App. No. 10/518,260
→
DATA CARRIER COMPRISING EVALUATION MEANS FOR EVALUATING INFORMATION REPRESENTED BY AN INFOMATION VOLTAGE
App. No. 10/516,845
→
DECOUPLING MODULE FOR DECOUPLING HIGH-FREQUENCY SIGNALS FROM A POWER SUPPLY LINE
App. No. 10/515,467
→
DIGITAL TO ANALOG CONVERSION
App. No. 10/511,974
→
METHOD OF PERFORMING ACCESS TO A SINGLE-PORT MEMORY DEVICE, MEMORY ACCESS DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD OF USE OF AN INTEGRATED CIRCUIT DEVICE
App. No. 10/512,031
→
VOLTAGE CONVERTER FOR CONVERTING AN INPUT VOLTAGE TO AN OUTPUT VOLTAGE AND DRIVING CIRCUIT COMPRISING A VOLTAGE CONVERTER
App. No. 10/511,479
→
CIRCUIT ARRANGEMENT FOR SHIFTING THE PHASE OF AN INPUT SIGNAL AND CIRCUIT ARRANGEMENT FOR SUPPRESSING THE MIRROR FREQUENCY
App. No. 10/508,456
→
FRONT STAGE AMPLIFIER WITH DIFFERENT MODES
App. No. 10/507,192
→
HIGH-FREQUENCY SIGNAL SWITCHING
App. No. 10/505,269
→