Data processing system with prefetching means

1. Data processing system, comprising:

at least one processor ( 12 ) for processing streaming data;

at least one cache memory ( 200 ) having a plurality of cache blocks ( 210 ), wherein one of said cache memories ( 200 ) is associated to each of said processors ( 12 ), and

at least one cache controller ( 300 ) for prefetching data into said cache memory ( 200 ), wherein one of said cache controllers ( 300 ) is associated to each of said cache memories ( 200 );

said cache controller ( 300 ) comprising:

determining means ( 350 ) for identifying at least one location in said cache memory ( 200 ) containing first data, which is predicted to be dismissible without penalty, said determining means being configured to determine if the last data word of first data words in a cache block ( 210 ) has been accessed by a reading operation from the at least one processor so that said first data words can be dismissed from the cache block; and

prefetch means ( 320 ) for issuing a prefetch operation replacing said first data at said location with second data which fit said location, said second data being prefetched from a memory ( 32 ), said prefetch means being configured to prefetch second data words from said memory, which replace said first data words in said cache block with said second data words, said second data words being of the same size as the first data words.

2. System according to claims 1 , wherein said data processing system is optimized for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources.

3. System according to claim 2 ,

wherein said determining means ( 350 ) is configured to perform the identification of said location restricted to a predetermined range of addresses.

4. System according to claim 1 , wherein

said prefetch means ( 320 ) is furthermore configured to prefetch said second data words from a second address in said memory ( 32 ), wherein said second address is the next higher address from a first address corresponding to the previous address of said first data words in said memory ( 32 ), and wherein said second data words fit said selected location of said first data words.

5. System according to claim 2 , wherein

said determining means ( 350 ) is configured to determine invalidated data words among first data words in said cache block ( 210 ), and

said prefetch means ( 320 ) is configured to prefetch second data words from said memory ( 32 ), which fit the location of said invalidated first data words in said cache block ( 210 ).

6. System according to claim 5 ,

wherein said first data words are reloaded from said memory ( 32 ).

7. System according to claim 2 , wherein

said determining means ( 350 ) is configured to determine if first data words in said cache block ( 210 ) do not belong to the stream of data currently operated by the processor, and

said prefetch means ( 320 ) is configured to prefetch second data words from a memory ( 32 ), which fit the location of said first data words in said cache block ( 210 ).

8. Method for prefetching data into a cache memory ( 200 ), wherein said cache memory ( 200 ) comprises a plurality of cache blocks ( 210 ), comprising the steps of:

a) identifying at least one location in said cache memory ( 200 ) containing first data, which is predicted to be dismissible without penalty, including determining if the last data word of first data words in a cache block has been accessed by a reading operation so that said first data words can be dismissed from the cache block; and then

b) issuing a prefetch operation by replacing said first data at said location with second data, which fit said location, said second data being prefetched from a memory ( 32 ), including prefetching second data words from said memory, which replace said first data words in said cache block with said second data words, said second data words being of the same size as the first data words.

9. Method according to claim 8 , wherein said method is performed in a data processing environment optimized for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources, wherein said cache memory ( 200 ) comprises a plurality of cache blocks.

10. Semiconductor means for use in a data processing environment optimized for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources, comprising:

a cache memory ( 200 ) having a plurality of cache blocks ( 210 ), and

a cache controller ( 300 ) for prefetching data into said cache memory ( 200 ), wherein said cache controller ( 300 ) is associated to said cache memories ( 200 );

said cache controller ( 300 ) comprising:

identification means ( 350 ) for identifying at least one location in said cache memory ( 200 ) containing first data, which is predicted to be dismissible without penalty, said identifying means being configured to determine if the last data word of first data words in a cache block ( 210 ) has been accessed by a reading operation so that said first data words can be dismissed from the cache block; and

prefetch means ( 320 ) for issuing a prefetch operation replacing said first data at said location with second data which fit said location, said second data being prefetched from a memory ( 32 ), said prefetch means being configured to prefetch second data words from said memory, which replace said first data words in said cache block with said second data words, said second data words being of the same size as the first data words.