Scannable synchronizer having a deceased resolving time
View Patent ↗The present invention provides a synchronizer for receiving an incoming data signal of a first clock domain and for outputting a data signal of a second clock domain. The synchronizer comprises an input stage, a master latch, a transfer stage and a slave latch. The input stage receives the data signal of the first clock domain and outputs the data signal to the master latch when the input stage is clocked with a master clock signal. The master latch stores the data signal at a storage node of the master latch. The master latch has a resolve time associated with it during which the master latch seeks to resolve the data signal to a logic 0 or a logic 1. The transfer stage transfers the data signal stored in the master latch to the slave latch when the transfer stage is clocked with a slave clock signal.
1. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
an input stage, the input stage receiving the incoming data signal of the first clock domain, the input stage comprising a clocked inverter, the input stage outputting an inverted data signal therefrom when the clocked inverter is clocked with a master clock signal M 1 ;
a master latch coupled to the input stage, the master latch receiving the inverted data signal output from the input stage and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
transfer logic coupled to the master latch, the transfer logic causing the signal stored in the master latch to be transferred out of the master latch when the transfer logic is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer logic, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .
2. The synchronizer of claim 1 , wherein the clocked inverter comprised by the input stage has a gain associated therewith and wherein the gain of the clocked inverter of the input stage reduces the likelihood that the data signal input to the master latch will have a value that places the master latch in a meta-stable state.
3. The synchronizer of claim 2 , wherein the transfer logic is a transfer stage comprising a clocked inverter, the clocked inverter of the transfer stage transferring a data signal out of the master latch and into the slave latch when the clocked inverter of the transfer stage is clocked with the slave clock signal S 1 , and wherein the clocked inverter of the transfer stage isolates the master latch from the slave latch while the master latch is seeking to resolve the data signal input to the master latch to a logic 0 or a logic 1.
4. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
input logic, the input logic receiving the incoming data signal of the first clock domain, the input logic outputting an inverted data signal therefrom when the input logic is clocked with a master clock signal M 1 ;
a master latch coupled to the input logic, the master latch receiving the inverted data signal output by the input logic and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
a transfer stage coupled to the master latch, the transfer stage comprising a clocked inverter, the transfer stage causing the signal stored in the master latch to be transferred out of the master latch when the clocked inverter of the transfer stage is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer stage, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .
5. The synchronizer of claim 4 , wherein the clocked inverter of the transfer stage isolates the master latch from the slave latch while the master latch is seeking to resolve the data signal stored in the master latch to a logic 0 or a logic 1.
6. The synchronizer of claim 4 , wherein the clocked inverter comprised by the transfer stage has a gain associated therewith and wherein the gain of the clocked inverter of the transfer stage reduces the likelihood that the data signal input to the slave latch will not resolve to a logic 0 or a logic 1.
7. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
an input stage, the input stage receiving the incoming data signal of the first clock domain, the input stage comprising a clocked inverter, the input stage outputting an inverted data signal therefrom when the clocked inverter is clocked with a master clock signal M 1 ;
a master latch coupled to the input stage, the master latch receiving the inverted data signal output from the input stage and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
transfer logic coupled to the master latch, the transfer logic causing the signal stored in the master latch to be transferred out of the master latch when the transfer logic is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer logic, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the master latch comprises:
a forward inverter, the forward inverter comprising an input terminal and an output terminal, the input terminal of the forward inverter being coupled to the storage node of the master latch, the output terminal of the forward inverter being coupled to an output node of the master latch, the output node of the master latch being coupled to the transfer logic;
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to the output node of the master latch;
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 ;
a second feedback inverter having an input terminal and an output terminal, the input terminal of the second feedback inverter being coupled to the output node of the master latch, the output terminal of the second feedback inverter being coupled to the storage node of the master latch; and
a transfer gate having a gate terminal, an input terminal and an output terminal, the output terminal of the transfer gate being connected to the storage node of the master latch, the input terminal of the transfer gate being connected to a test port of the synchronizer, the transfer gate controlling a transfer of test data received at the test port into the master latch, the gate terminal of the transfer gate being coupled to a shift control signal that is capable of turning the transfer gate on and off for controlling the transfer of data from the test port into the master latch, wherein when the shift control signal turns the transfer gate on, said transmission gate clock signal CK turns said transmission gate off such that the first feedback inverter is inoperative.
8. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
an input stage, the input stage receiving the incoming data signal of the first clock domain, the input stage comprising a clocked inverter, the input stage outputting an inverted data signal therefrom when the clocked inverter is clocked with a master clock signal M 1 ;
a master latch coupled to the input stage, the master latch receiving the inverted data signal output from the input stage and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
transfer logic coupled to the master latch, the transfer logic causing the signal stored in the master latch to be transferred out of the master latch when the transfer logic is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer logic, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal the second clock domain;
wherein the clocked inverter comprised by the input stage has a gain associated therewith and wherein the gain of the clocked inverter of the input stage reduces the likelihood that the data signal input to the master latch will have a value that places the master latch in a meta-stable state;
wherein the clocked inverter comprised by the input stage comprises two P field effect transistors (PFETs) and two N field effect transistors (NFETs), each of the PFETs and NFETs having a gate terminal, a first channel terminal and a second channel terminal, the first channel terminal of a first one of the PFETs being connected to a supply voltage, the first channel terminal of a second one of the PFETs being connected to the second channel terminal of the first PFET, the first channel terminal of a first one of the NFETs being connected to the second channel terminal of the second PFET, the first channel terminal of a second one of the NFETs being connected to the second channel terminal of the first NFET, the second channel terminal of the second NFET being connected to ground, the data signal received by the input stage being applied to the gate terminals of the first PFET and the second NFET, the master clock signal being applied to the gate terminal of the first NFET, an inverse of the master clock signal being applied to a gate terminal of the second PFET, the storage node of the master latch corresponding to the connection between the second PFET and the first NFET; and
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .
9. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
an input stage, the input stage receiving the incoming data signal of the first clock domain, the input stage comprising a clocked inverter, the input stage outputting an inverted data signal therefrom when the clocked inverter is clocked with a master clock signal M 1 ;
a master latch coupled to the input stage, the master latch receiving the inverted data signal output from the input stage and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
transfer logic coupled to the master latch, the transfer logic causing the signal stored in the master latch to be transferred out of the master latch when the transfer logic is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer logic, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the clocked inverter comprised by the input stage has a gain associated therewith and wherein the gain of the clocked inverter of the input stage reduces the likelihood that the data signal input to the master latch will have a value that places the master latch in a meta-stable state;
wherein the transfer logic is a transfer stage comprising a clocked inverter, the clocked inverter of the transfer stage transferring a data signal out of the master latch and into the slave latch when the clocked inverter of the transfer stage is clocked with the slave clock signal S 1 , and wherein the clocked inverter of the transfer stage isolates the master latch from the slave latch while the master latch is seeking to resolve the data signal input to the master latch to a logic 0 or a logic 1; and
wherein the clocked inverter of the transfer stage comprises two P field effect transistors (PFETs) and two N field effect transistors (NFETs), each of the PFETs and NFETs having a gate terminal, a first channel terminal and a second channel terminal, the first channel terminal of a first one of the PFETs being connected to a supply voltage, the first channel terminal of a second one of the PFETs being connected to the second channel terminal of the first PFET, the first channel terminal of a first one of the NFETs being connected to the second channel terminal of the second PFET, the first channel terminal of a second one of the NFETs being connected to the second channel terminal of the first NFET, the second channel terminal of the second NFET being connected to ground, the data signal received by the transfer stage being applied to the gate terminals of the first PFET and the second NFET, the slave clock signal being applied to the gate terminal of the first NFET, an inverse of the slave clock signal being applied to a gate terminal of the second PFET, the storage node of the slave latch corresponding to the connection between the second PFET and the first NFET; and
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .
10. The synchronizer of claim 9 , wherein the slave latch comprises:
a first forward inverter, the first forward inverter comprising an input terminal and an output terminal, the input terminal of the first forward inverter being coupled to a storage node of the slave latch;
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to the output terminal of the first forward inverter;
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the slave latch, the transmission gate being controlled by the slave clock signal S 1 ;
a second feedback inverter having an input terminal and an output terminal, the input terminal of the second feedback inverter being coupled to the output terminal of the first forward inverter, the output terminal of the second feedback inverter being coupled to the storage node of the slave latch; and
second forward inverter having an input terminal and an output terminal, the input terminal of the second forward inverter being coupled to the storage node of the slave latch, the output terminal of the second forward inverter corresponding to the output terminal of the synchronizer slave latch.
11. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
input logic, the input logic receiving the incoming data signal of the first clock domain, the input logic outputting an inverted data signal therefrom when the input logic is clocked with a master clock signal M 1 ;
a master latch coupled to the input logic, the master latch receiving the inverted data signal output by the input logic and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
a transfer stage coupled to the master latch, the transfer stage comprising a clocked inverter, the transfer stage causing the signal stored in the master latch to be transferred out of the master latch when the clocked inverter of the transfer stage is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer stage, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal the second clock domain;
wherein the master latch comprises:
a forward inverter, the forward inverter comprising an input terminal and an output terminal, the input terminal of the forward inverter being coupled to the storage node of the master latch, the output terminal of the forward inverter being coupled to an output node of the master latch, the output node of the master latch being coupled to the transfer stage;
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to the output node of the master latch;
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 ;
a second feedback inverter having an input terminal and an output terminal, the input terminal of the second feedback inverter being coupled to the output node of the master latch, the output terminal of the second feedback inverter being coupled to the storage node of the master latch; and
a transfer gate having a gate terminal, an input terminal and an output terminal, the output terminal of the transmission gate being connected to the storage node of the master latch, the input terminal of the transfer gate being connected to a test port of the synchronizer, the transfer gate controlling a transfer of test data received at the test port into the master latch, the gate terminal of the transfer gate being coupled to a shift control signal that is capable of turning the transfer gate on and off for controlling the transfer of data from the test port into the master latch, wherein when the shift control signal turns the transmission gate on, said transmission gate clock signal CK turns said transmission gate off such that the first feedback inverter is inoperative.
12. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
input logic, the input logic receiving the incoming data signal of the first clock domain, the input logic outputting an inverted data signal therefrom when the input logic is clocked with a master clock signal M 1 ;
a master latch coupled to the input logic, the master latch receiving the inverted data signal output by the input logic and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
a transfer stage coupled to the master latch, the transfer stage comprising a clocked inverter, the transfer stage causing the signal stored in the master latch to be transferred out of the master latch when the clocked inverter of the transfer stage is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer stage, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the slave latch comprises:
a first forward inverter, the first forward inverter comprising an input terminal and an output terminal, the input terminal of the forward inverter being coupled to a storage node of the slave latch;
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to the output terminal of the first forward inverter;
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the slave latch, the transmission gate being controlled by the slave clock signal S 1 ;
a second feedback inverter having an input terminal and an output terminal, the input terminal of the second feedback inverter being coupled to the output terminal of the first forward inverter, the output terminal of the second feedback inverter being coupled to the storage node of the slave latch; and
a second forward inverter having an input terminal and an output terminal, the input terminal of the second forward inverter being coupled to the storage node of the slave latch, the output terminal of the second forward inverter corresponding to the output terminal of the slave latch; and
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .
13. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
input logic, the input logic receiving the incoming data signal of the first clock domain, the input logic outputting an inverted data signal therefrom when the input logic is clocked with a master clock signal M 1 ;
a master latch coupled to the input logic, the master latch receiving the inverted data signal output by the input logic and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
a transfer stage coupled to the master latch, the transfer stage comprising a clocked inverter, the transfer stage causing the signal stored in the master latch to be transferred out of the master latch when the clocked inverter of the transfer stage is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer stage, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the clocked inverter of the transfer stage comprises two P field effect transistors (PFETs) and two N field effect transistors (NFETs), each of the PFETs and NFETs having a gate terminal, a first channel terminal and a second channel terminal, the first channel terminal of a first one of the PFETs being connected to a supply voltage, the first channel terminal of a second one of the PFETs being connected to the second channel terminal of the first PFET, the first channel terminal of a first one of the NFETs being connected to the second channel terminal of the second PFET, the first channel terminal of a second one of the NFETs being connected to the second channel terminal of the first NFET, the second channel terminal of the second NFET being connected to ground, the data signal received by the transfer stage being applied to the gate terminals of the first PFET and the second NFET, the slave clock signal being applied to the gate terminal of the first NFET, an inverse of the slave clock signal being applied to a gate terminal of the second PFET, the storage node of the slave latch corresponding to the connection between the second PFET and the first NFET; and
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .
14. A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising:
input logic, the input logic receiving the incoming data signal of the first clock domain, the input logic outputting an inverted data signal therefrom when the input logic is clocked with a master clock signal M 1 ;
a master latch coupled to the input logic, the master latch receiving the inverted data signal output by the input logic and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1;
a transfer stage coupled to the master latch, the transfer stage comprising a clocked inverter, the transfer stage causing the data signal stored in the master latch to be transferred out of the master latch when the clocked inverter of the transfer stage is clocked with a slave clock signal S 1 ; and
a slave latch coupled to the transfer stage, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain;
wherein the input logic comprises a field effect transistor (FET) having a gate terminal, a first channel terminal and a second channel terminal, the gate terminal of FET being connected to the master clock signal M 1 , the data signal received by the input logic being received at the first channel terminal of the FET, the second channel terminal of the FET being connected to the storage node of the master latch; and
wherein the master latch comprises:
a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and
a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .