Patent Assignment
Reel/Frame 048555/0510
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER.
Recorded: 2019-03-06
Received: 2019-03-06
Pages: 110
Assignor
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Executed: 2018-09-05
Assignee
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
1 YISHUN AVENUE 7, SINGAPORE, SGX, 768923, SINGAPORE
Covered Applications
(100)
RESISTOR LADDER INTERPOLATION FOR SUBRANGING ADC
App. No. 11/651,454
→
METHOD FOR TRANSCONDUCTANCE LINEARIZATION FOR DC-COUPLED APPLICATIONS
App. No. 11/599,247
→
ADAPTABLE VOLTAGE CONTROL FOR A VARIABLE GAIN AMPLIFIER
App. No. 11/559,195
→
INTERLOCKING MEMORY/LOGIC CELL LAYOUT AND METHOD OF MANUFACTURE
App. No. 11/585,460
→
USE OF A THICK OXIDE DEVICE AS A CASCODE FOR A THIN OXIDE TRANSCONDUCTANCE DEVICE IN MOSFET TECHNOLOGY AND ITS APPLICATION TO A POWER AMPLIFIER DESIGN
App. No. 11/582,022
→
APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL
App. No. 11/534,870
→
CAM-BASED SEARCH ENGINES THAT SUPPORT PIPELINED MULTI-DATABASE SEARCH OPERATIONS USING ENCODED MULTI-DATABASE IDENTIFIERS
App. No. 11/532,746
→
CANCELLATION OF INTERFERENCE IN A COMMUNICATION SYSTEM WITH APPLICATION TO S-CDMA
App. No. 11/522,837
→
HIGH SPEED CMOS TRANSMIT-RECEIVE ANTENNA SWITCH
App. No. 11/516,414
→
DUAL LINK DVI TRANSMITTER SERVICED BY SINGLE PHASE LOCKED LOOP
App. No. 11/516,301
→
AMBIGUOUS VIRTUAL CHANNELS
App. No. 11/514,119
→
METHODS AND SYSTEMS TO PROVIDE A PLURALITY OF SIGNALS HAVING RESPECTIVE DIFFERENT PHASES
App. No. 11/496,421
→
APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL USING UNIT CURRENT SOURCES
App. No. 11/459,205
→
ENCODER INTERPOLATION APPARATUS
App. No. 11/439,352
→
OPTICAL POSITION SENSING DEVICE
App. No. 11/436,337
→
GIGABIT ETHERNET TRANSCEIVER WITH ANALOG FRONT END
App. No. 11/417,073
→
VIA PROVIDING MULTIPLE ELECTRICALLY CONDUCTIVE PATHS
App. No. 11/400,217
→
HIGH EFFICIENCY POWER AMPLIFIER
App. No. 11/396,297
→
CONTENT ADDRESSABLE MEMORY (CAM) DEVICES HAVING PRIORITY CLASS DETECTORS THEREIN THAT PERFORM LOCAL ENCODING OF MATCH LINE SIGNALS
App. No. 11/393,336
→
CURRENT-CONTROLLED CMOS LOGIC FAMILY
App. No. 11/385,632
→
PHYSICAL LAYER LOOP BACK METHOD AND APPARATUS
App. No. 11/384,516
→
REFLECTIVE LINEAR ENCODER HAVING CONTROLLED DETECTOR TO CODE STRIP DISTANCE
App. No. 11/378,007
→
CONTINUOUS-TIME DELTA-SIGMA ADC FOR A RADIO RECEIVER EMPLOYING 200 KHZ IF
App. No. 11/369,045
→
FIBER OPTIC TRANSCEIVER MODULE WITH ELECTROMAGNETIC INTERFERENCE ABSORBING MATERIAL AND METHOD FOR MAKING THE MODULE
App. No. 11/368,250
→
DATA ACCESS IN A PROCESSOR
App. No. 11/364,927
→
BIASING SCHEME FOR LOW SUPPLY HEADROOM APPLICATIONS
App. No. 11/364,030
→
USE OF A DOWN-BOND AS A CONTROLLED INDUCTOR IN INTEGRATED CIRCUIT APPLICATIONS
App. No. 11/353,910
→
TRANSCONDUCTANCE / C COMPLEX BAND-PASS FILTER
App. No. 11/348,893
→
METHOD AND SYSTEM FOR CONVERTING DIGITAL SAMPLES TO AN ANALOG SIGNAL
App. No. 11/342,658
→
DECISION FEEDBACK EQUALIZER FOR MINIMUM AND MAXIMUM PHASE CHANNELS
App. No. 11/344,406
→
TWO DIMENSIONAL DATA ACCESS IN A PROCESSOR
App. No. 11/333,574
→
SYSTEM AND METHOD FOR COMPENSATING FOR THE EFFECTS OF PROCESS, VOLTAGE, AND TEMPERATURE VARIATIONS IN A CIRCUIT
App. No. 11/328,175
→
APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL USING UNIT CURRENT SOURCES
App. No. 11/314,618
→
METHOD AND APPARATUS FOR COMPENSATING AN OSCILLATOR IN A LOCATION-ENABLED WIRELESS DEVICE
App. No. 11/311,088
→
CONTINUOUS-TIME DELTA-SIGMA ADC WITH PROGRAMMABLE INPUT RANGE
App. No. 11/301,513
→
PACKAGE FOR A HIGH-FREQUENCY ELECTRONIC DEVICE
App. No. 10/560,004
→
NARROW/WIDE CACHE
App. No. 11/299,264
→
INTERPOLATING ENCODER UTILIZING A FREQUENCY MULTIPLIER
App. No. 11/292,961
→
METHODS AND APPARATUS FOR ACCELERATING SECURE SESSION PROCESSING
App. No. 11/286,111
→
HIGH-SPEED SAMPLING ARCHITECTURES
App. No. 11/284,985
→
PSEUDO TERNARY CONTENT ADDRESSABLE MEMORY DEVICE HAVING ROW REDUNDANCY AND METHOD THEREFOR
App. No. 11/281,227
→
AMPLIFIER CIRCUIT, AND SYSTEM INCORPORATING SAME
App. No. 11/282,455
→
SYSTEM AND METHOD FOR PRODUCING WHITE LIGHT USING A COMBINATION OF PHOSPHOR-CONVERTED WHITE LEDS AND NON-PHOSPHOR-CONVERTED COLOR LEDS
App. No. 11/273,122
→
SCRAMBLED BLOCK ENCODER
App. No. 11/267,184
→
FULLY DIFFERENTIAL INPUT BUFFER WITH WIDE SIGNAL SWING RANGE
App. No. 11/266,207
→
METHOD AND APPARATUS FOR MITIGATING MULTIPATH EFFECTS AT A SATELLITE SIGNAL RECEIVER USING A SEQUENTIAL ESTIMATION FILTER
App. No. 11/259,767
→
PULSE STRETCHING ARCHITECTURE FOR PHASE ALIGNMENT FOR HIGH SPEED DATA ACQUISITION
App. No. 11/256,156
→
MODULATION DEPENDENT BIASING FOR EFFICIENT AND HIGH LINEARITY POWER AMPLIFIERS
App. No. 11/247,852
→
LOW POWER, HIGH SNR, HIGH ORDER DELTA SIGMA MODULATOR STAGE HAVING INTEGRATORS WITH PIPELINED CROSS COUPLED INPUT CIRCUITS
App. No. 11/246,615
→
CONVERTING DUAL PORT MEMORY INTO 2 SINGLE PORT MEMORIES
App. No. 11/243,622
→
COLUMN DEFECT DETECTION IN A CONTENT ADDRESSABLE MEMORY
App. No. 11/240,160
→
LATCH-BASED RANDOM ACCESS MEMORY (LBRAM) WITH TRI-STATE BANKING AND CONTENTION AVOIDANCE
App. No. 11/237,059
→
LATCH-BASED RANDOM ACCESS MEMORY (LBRAM) TRI-STATE BANKING ARCHITECTURE
App. No. 11/237,064
→
ROBUST AND SCALABLE DE-SKEW METHOD FOR DATA PATH SKEW CONTROL
App. No. 11/231,773
→
SYSTEM AND METHOD FOR EMITTING AND DETECTING LIGHT USING LIGHT EMITTING DIODE
App. No. 11/230,708
→
SECURITY CHIP ARCHITECTURE AND IMPLEMENTATIONS FOR CRYPTOGRAPHY ACCELERATION
App. No. 11/229,457
→
COMPRESSED AUDIO STREAM DATA DECODER MEMORY SHARING TECHNIQUES
App. No. 11/224,202
→
SYNCHRONIZING AN ASYNCHRONOUSLY DETECTED SERVO SIGNAL TO SYNCHRONOUS SERVO DEMODULATION
App. No. 11/223,090
→
CLOCK GENERATOR HAVING A 50% DUTY-CYCLE
App. No. 11/222,631
→
STRIPLINE STRUCTURE
App. No. 11/222,268
→
DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE CURRENT CONTROL
App. No. 11/214,798
→
METHODS AND SYSTEMS FOR BATTERY CHARGING CONTROL BASED ON CMOS TECHNOLOGY
App. No. 11/206,180
→
REDUCTION OF AGGREGATE EMI EMISSIONS OF MULTIPLE TRANSMITTERS
App. No. 11/204,530
→
SYSTEM AND METHOD FOR DETECTING A DEVICE REQUIRING POWER
App. No. 11/204,529
→
SLICER WITH LARGE INPUT COMMON MODE RANGE
App. No. 11/204,113
→
APPARATUS AND METHOD OF IMAGE PROCESSING TO AVOID IMAGE SATURATION
App. No. 11/203,287
→
DECODING TECHNIQUES FOR MULTI-ANTENNA SYSTEMS
App. No. 11/195,184
→
SYNCHRONOUS GLOBAL CONTROLLER FOR ENHANCED PIPELINING
App. No. 11/191,803
→
METHOD AND APPARATUS FOR IMPROVING BUS MASTER PERFORMANCE
App. No. 11/189,688
→
METHOD AND/OR APPARATUS FOR TRANSCODING BETWEEN H.264 CABAC AND CAVLC ENTROPY CODING MODES
App. No. 11/183,580
→
SYSTEM TO ACCELERATE SETTLING OF AN AMPLIFIER
App. No. 11/182,972
→
MULTIPLE MOVEMENTS HARMONIC FREQUENCY ACTUATOR SYSTEM
App. No. 11/182,175
→
LOW COST OPTICAL AMPLIFIER
App. No. 11/181,307
→
CONTENT ADDRESSABLE MEMORY (CAM) ARRAYS HAVING MEMORY CELLS THEREIN WITH DIFFERENT SUSCEPTIBILITIES TO SOFT ERRORS
App. No. 11/181,534
→
NETWORK INTERFACE USING PROGRAMMABLE DELAY AND FREQUENCY DOUBLER
App. No. 11/180,628
→
METHOD OF HANDLING DATA IN A NETWORK DEVICE
App. No. 11/176,353
→
LIGHT MODULATING INPUT DEVICE FOR CAPTURING USER CONTROL INPUTS
App. No. 11/175,757
→
SYSTEM AND METHOD FOR ESD PROTECTION
App. No. 11/171,325
→
METHOD FOR PLACING METAL CONTACTS UNDERNEATH FBAR RESONATORS
App. No. 11/174,364
→
LOW-POWER SUPPLY VOLTAGE LEVEL DETECTION CIRCUIT AND METHOD
App. No. 11/169,012
→
WIDEBAND CMOS GAIN STAGE
App. No. 11/165,493
→
MULTI-MODE INTEGRATED CIRCUIT STRUCTURE
App. No. 11/165,865
→
APPARATUS FOR IMPROVED CONNECTOR LAYOUT
App. No. 11/154,666
→
CONTENT ADDRESSABLE MEMORY WITH PROGRAMMABLE WORD WIDTH AND PROGRAMMABLE PRIORITY
App. No. 11/154,066
→
POWER REDUCTION
App. No. 11/152,382
→
COLORED NOISE DETECTION ALGORITHMS
App. No. 11/150,931
→
NETWORK INTERFACE WITH DOUBLE DATA RATE AND DELAY LOCKED LOOP
App. No. 11/149,182
→
BANDPASS FILTER NETWORK AND METHOD FOR BANDPASS FILTERING SIGNALS USING MULTIPLE ACOUSTIC RESONATORS
App. No. 11/150,497
→
SEMI-SUSPENDED COPLANAR WAVEGUIDE ON A PRINTED CIRCUIT BOARD
App. No. 11/148,564
→
CONTENT COMPARATOR MEMORY (CCM) DEVICE AND METHOD OF OPERATION
App. No. 11/146,639
→
METHODS AND APPARATUS FOR REDUCING OUTPUT CURRENT OSCILLATIONS OF A DRIVER PROVIDED WITH CIRCUITRY THAT SENSES AND RESPONDS TO EXCESSIVE CURRENT DRAWS OF AN OUTPUT STAGE OF THE DRIVER
App. No. 11/147,795
→
COMPACT BALUN WITH REJECTION FILTER FOR 802.11A AND 802.11B SIMULTANEOUS OPERATION
App. No. 11/138,317
→
MULTIPLE PHASE DETECTION FOR DELAY LOOPS
App. No. 11/138,703
→
HIGH SPEED NAND-TYPE CONTENT ADDRESSABLE MEMORY (CAM)
App. No. 11/137,163
→
SELECTABLE TRAINING SIGNALS BASED ON STORED PREVIOUS CONNECTION INFORMATION FOR DMT-BASED SYSTEM
App. No. 11/132,147
→
PIEZOELECTRICALLY-ACTIVATED CANTILEVERED SPATIAL LIGHT MODULATOR
App. No. 11/131,706
→
SYSTEM AND METHOD FOR LINEARIZING A CMOS DIFFERENTIAL PAIR
App. No. 11/131,281
→
MONOLITHIC LIVING HINGE SMALL FORM FACTOR TRANSCEIVER BAIL-DELATCH
App. No. 11/129,138
→
SYSTEM AND METHOD FOR DETECTING A DEVICE REQUIRING POWER
App. No. 11/125,912
→
CURRENT-CONTROLLED CMOS CIRCUITS WITH INDUCTIVE BROADBANDING
App. No. 11/125,455
→