Multiple phase detection for delay loops
A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.
1. Circuitry comprising:
a delay loop having a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal, wherein the delay loop forms a closed loop in which each delay element in the delay loop is connected to (1) receive an upstream output clock signal from a previous delay element in the delay loop and (2) provide a downstream output clock signal to a subsequent delay element in the delay loop;
a first phase detector adapted to characterize phase difference between a first pair of the output clock signals to generate a first phase-difference result;
a second phase detector adapted to characterize phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
a comparator adapted to compare the first and second phase-difference results to generate a control signal for adjusting delay of each delay element.
2. The circuitry of claim 1 , wherein the comparator is adapted to generate the control signal to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased.
3. The circuitry of claim 2 , wherein the comparator is adapted to generate a null control signal if the first and second phase-difference results do not agree.
4. The circuitry of claim 2 , wherein the comparator is adapted to repeat a previous control signal if the first and second phase-difference results do not agree.
5. The circuitry of claim 1 , further comprising a filter adapted to filter the control signal generated by the comparator.
6. The circuitry of claim 5 , wherein:
the control signal is a digital control signal;
the filter is a digital filter adapted to digitally filter the digital control signal generated by the comparator; and
further comprising a digital-to-analog converter adapted to convert the filtered digital control signal into an analog current control signal used to control the delays by the delay elements.
7. The circuitry of claim 1 , wherein:
the delay loop is part of a receiver;
the output clock signals from the delay elements are adapted to be used to sample a data signal received by the receiver; and
the delay loop is adapted to control the delays by the delay elements in order to match bulk delay of the delay elements with a period of an input clock signal applied to the delay loop.
8. The circuitry of claim 1 , wherein:
the comparator is adapted to generate the control signal to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased;
the comparator is adapted to generate a null control signal if the first and second phase-difference results do not agree;
further comprising:
a digital filter adapted to filter the control signal generated by the comparator; and
a digital-to-analog converter adapted to convert the filtered control signal into an analog current control signal used to control the delays by the delay elements;
the delay loop is part of a receiver;
the output clock signals from the delay elements are adapted to be used to sample a data signal received by the receiver; and
the delay loop is adapted to control the delays by the delay elements in order to match bulk delay of the delay elements with a period of an input clock signal applied to the delay loop.
9. The circuitry of claim 1 , wherein the first and second pairs of output clock signals do not have any output clock signal in common.
10. A method for operating circuitry comprising a delay loop comprising a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal, wherein the delay loop forms a closed loop in which each delay element in the delay loop is connected to (1) receive an upstream output clock signal from a previous delay element in the delay loop and (2) provide a downstream output clock signal to a subsequent delay element in the delay loop, the method comprising:
characterizing phase difference between a first pair of the output clock signals to generate a first phase-difference result;
characterizing phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
comparing the first and second phase-difference results to generate a control signal for adjusting delay of each delay element.
11. The method of claim 10 , wherein:
the delay loop is part of a receiver;
the output clock signals from the delay elements are used to sample a data signal received by the receiver; and
the delay loop is adapted to control the delays by the delay elements in order to match bulk delay of the delay elements with a period of an input clock signal applied to the delay loop.
12. The method of claim 10 , wherein:
the control signal is generated to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased;
a null control signal is generated if the first and second phase-difference results do not agree;
further comprising:
filtering the control signal; and
converting the filtered control signal into an analog current control signal used to control the delays by the delay elements;
the delay loop is part of a receiver;
the output clock signals from the delay elements are used to sample a data signal received by the receiver; and
the delay loop controls the delays by the delay elements in order to match bulk delay of the delay elements with a period of an input clock signal applied to the delay loop.
13. The method of claim 10 , further comprising filtering the control signal generated by the comparator.
14. The method of claim 13 , wherein:
the control signal is a digital control signal;
the filtering is digital filtering of the digital control signal; and
further comprising converting the filtered digital control signal into an analog current control signal used to control the delays by the delay elements.
15. The method of claim 10 , wherein the control signal is generated to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased.
16. The method of claim 15 , wherein a null control signal is generated if the first and second phase-difference results do not agree.
17. The method of claim 15 , wherein a previous control signal is repeated if the first and second phase-difference results do not agree.
18. The method of claim 10 , wherein the first and second pairs of output clock signals do not have any output clock signal in common.
19. Circuitry comprising:
a delay loop having a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal;
a first phase detector adapted to characterize phase difference between a first pair of the output clock signals to generate a first phase-difference result;
a second phase detector adapted to characterize phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
a comparator adapted to compare the first and second phase-difference results to generate a control signal for adjusting delay of each delay element, wherein:
the comparator is adapted to generate the control signal to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased; and
the comparator is adapted to generate a null control signal if the first and second phase-difference results do not agree.
20. Circuitry comprising:
a delay loop having a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal;
a first phase detector adapted to characterize phase difference between a first pair of the output clock signals to generate a first phase-difference result;
a second phase detector adapted to characterize phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
a comparator adapted to compare the first and second phase-difference results to generate a control signal for adjusting delay of each delay element, wherein:
the comparator is adapted to generate the control signal to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased; and
the comparator is adapted to repeat a previous control signal if the first and second phase-difference results do not agree.
21. Circuitry comprising:
a delay loop having a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal;
a first phase detector adapted to characterize phase difference between a first pair of the output clock signals to generate a first phase-difference result;
a second phase detector adapted to characterize phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result;
a comparator adapted to compare the first and second phase-difference results to generate a control signal for adjusting delay of each delay element; and
a filter adapted to filter the control signal generated by the comparator.
22. The circuitry of claim 21 , wherein:
the control signal is a digital control signal;
the filter is a digital filter adapted to digitally filter the digital control signal generated by the comparator; and
further comprising a digital-to-analog converter adapted to convert the filtered digital control signal into an analog current control signal used to control the delays by the delay elements.
23. Circuitry comprising:
a delay loop having a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal;
a first phase detector adapted to characterize phase difference between a first pair of the output clock signals to generate a first phase-difference result;
a second phase detector adapted to characterize phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
a comparator adapted to compare the first and second phase-difference results to generate a control signal for adjusting delay of each delay element, wherein:
the delay loop is part of a receiver;
the output clock signals from the delay elements are adapted to be used to sample a data signal received by the receiver; and
the delay loop is adapted to control the delays by the delay elements in order to match bulk delay of the delay elements with a period of an input clock signal applied to the delay loop.
24. A method for operating circuitry comprising a delay loop comprising a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal, the method comprising:
characterizing phase difference between a first pair of the output clock signals to generate a first phase-difference result;
characterizing phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
comparing the first and second phase-difference results to generate a control signal for adjusting delay of each delay element, wherein:
the control signal is generated to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased; and
a null control signal is generated if the first and second phase-difference results do not agree.
25. A method for operating circuitry comprising a delay loop comprising a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal, the method comprising:
characterizing phase difference between a first pair of the output clock signals to generate a first phase-difference result;
characterizing phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
comparing the first and second phase-difference results to generate a control signal for adjusting delay of each delay element, wherein:
the control signal is generated to:
increase the delay applied by the delay elements if the first and second phase-difference results indicate that the delay should be increased; and
decrease the delay if the first and second phase-difference results indicate that the delay should be decreased; and
a previous control signal is repeated if the first and second phase-difference results do not agree.
26. A method for operating circuitry comprising a delay loop comprising a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal, the method comprising:
characterizing phase difference between a first pair of the output clock signals to generate a first phase-difference result;
characterizing phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result;
comparing the first and second phase-difference results to generate a control signal for adjusting delay of each delay element; and
filtering the control signal generated by the comparator.
27. The method of claim 26 , wherein:
the control signal is a digital control signal;
the filtering is digital filtering of the digital control signal; and
further comprising converting the filtered digital control signal into an analog current control signal used to control the delays by the delay elements.
28. A method for operating circuitry comprising a delay loop comprising a plurality of sequentially arranged delay elements, each adapted to generate a corresponding output clock signal, the method comprising:
characterizing phase difference between a first pair of the output clock signals to generate a first phase-difference result;
characterizing phase difference between a second pair of the output clock signals different from the first pair to generate a second phase-difference result; and
comparing the first and second phase-difference results to generate a control signal for adjusting delay of each delay element, wherein:
the delay loop is part of a receiver;
the output clock signals from the delay elements are used to sample a data signal received by the receiver; and
the delay loop is adapted to control the delays by the delay elements in order to match bulk delay of the delay elements with a period of an input clock signal applied to the delay loop.