IP Library Granted Patent US 7,265,632
Granted Patent B2
US 7,265,632 · App. 11/282,455 · Granted Sep 4, 2007

Amplifier circuit, and system incorporating same

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Quick Facts
Patent No.
US 7,265,632
App. No.
11/282,455
Granted
Sep 4, 2007
Kind
B2
Abstract

In one embodiment, a current source circuit having a reference resistor produces first, second and third bias currents that vary with manufacturing variances of the current compensation resistor. An input amplification stage includes a transconductance stage biased by the first bias current, a first transimpedance amplifier (TIA) biased by the second bias current, and a first feedback resistor coupled between the first TIA's input and output. The input of the first TIA is coupled to an output of the transconductance stage. An output amplification stage is biased by the third bias current and has an input coupled to an output of the first TIA. A second feedback resistor is coupled between the output of the output amplification stage and the input of the transconductance stage. The reference resistor and first and second feedback resistors are formed using a common manufacturing process.

Claims (16)

1. An amplifier circuit, comprising:

a current source circuit having a reference resistor, the current source circuit producing first, second and third bias currents that vary with manufacturing variances of the reference resistor;

an input amplification stage comprising i) a transconductance stage biased by the first bias current, and ii) a first transimpedance amplifier (TIA) biased by the second bias current, the first TIA having a first feedback resistor coupled between its input and its output, and the input of the first TIA being coupled to an output of the transconductance stage;

an output amplification stage biased by the third bias current, the output amplification stage having an input coupled to an output of the first TIA; and

a second feedback resistor, coupled between the output of the output amplification stage and the input of the transconductance stage to form a second TIA; wherein the reference resistor, the first feedback resistor and the second feedback resistor are formed using a common manufacturing process.

2. The amplifier circuit of claim 1 , wherein the transconductance stage, the first TIA and the output amplification stage each comprise a single metal-oxide semiconductor (MOS) transistor, with a gate of the transistor serving as the stage's input, and with a drain of the transistor serving as the stage's output.

3. The amplifier circuit of claim 2 , wherein the current source circuit comprises a plurality of MOS transistors; and wherein the MOS transistors of the current source circuit, the transconductance stage, the first TIA and the output amplification stage are all formed using a common manufacturing process.

4. A light sensing system, comprising:

a photosensor;

a current source circuit having a reference resistor, the current source circuit producing first, second and third bias currents that vary with manufacturing variances of the reference resistor;

an input amplification stage comprising i) a transconductance stage biased by the first bias current, the transconductance stage having an input coupled to an output of the photosensor, and ii) a first transimpedance amplifier (TIA) biased by the second bias current, the first TIA having a first feedback resistor coupled between its input and its output, and the input of the first TIA being coupled to an output of the transconductance stage;

an output amplification stage biased by the third bias current, the output amplification stage having an input coupled to an output of the first TIA; and

a second feedback resistor, coupled between the output of the output amplification stage and the input of the transconductance stage to form a second TIA; wherein the reference resistor, the first feedback resistor and the second feedback resistor are formed using a common manufacturing process.

5. The light sensing system of claim 4 , wherein the photosensor is a photodiode.

6. The light sensing system of claim 4 , wherein the transconductance stage, the first TIA and the output amplification stage each comprise a single metal-oxide semiconductor (MOS) transistor, with a gate of the transistor serving as the stage's input, and with a drain of the transistor serving as the stage's output.

7. The light sensing system of claim 6 , wherein the current source circuit comprises a plurality of MOS transistors; and wherein the MOS transistors of the current source circuit, the transconductance stage, the first TIA and the output amplification stage are all formed using a common manufacturing process.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
Reel/Frame 017675/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2006
From: KWA, HOCK TIONG; JI, XUE MIN; ZHANG, BIN; CHAN, PAK KWONG
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 017160/0994 →