Current-controlled CMOS logic family
View Patent ↗Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C 3 MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C 3 MOS logic with low power conventional CMOS logic. The combined C 3 MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
1. An apparatus, comprising:
a first circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process a first signal thereby generating a second signal there from, wherein the first signal is a differential signal;
a second circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process a third signal thereby generating a fourth signal there from, wherein the second signal is a differential signal; and
a third circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to:
receive the second signal;
receive the fourth signal; and
process the second signal and the fourth signal thereby generating a fifth signal there from.
2. The apparatus of claim 1 , wherein:
the fifth signal is a serialized signal that includes information contained within the second signal and the fourth signal.
3. The apparatus of claim 1 , wherein:
the first signal has a first frequency;
the second signal has the first frequency; and
the fifth signal has a second frequency.
4. The apparatus of claim 1 , wherein:
the first signal has a first frequency;
the second signal has the first frequency;
the fifth signal has a second frequency; and
the second frequency is greater than the first frequency.
5. The apparatus of claim 1 , wherein:
the first signal has a first frequency;
the second signal has the first frequency;
the fifth signal has a second frequency; and
the second frequency is an integer multiple of the first frequency.
6. The apparatus of claim 1 , further comprising:
a fourth circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a sixth signal thereby generating the first signal and the third signal there from.
7. The apparatus of claim 6 , wherein:
the first signal has a first frequency;
the second signal has the first frequency; and
the fifth signal has a second frequency; and
the sixth signal has the second frequency.
8. The apparatus of claim 1 , wherein:
the first circuit block, the second circuit block, and the third circuit block are all implemented on a single silicon die.
9. An apparatus, comprising:
a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a first signal thereby generating a second signal and a third signal there from;
a second circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process the second signal thereby generating a fourth signal there from; and
a third circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the third signal thereby generating a fifth signal there from.
10. The apparatus of claim 9 , wherein:
the first circuit block deserializes the first signal thereby generating the second signal and the third signal there from such that the second signal includes first information contained within the first signal and the third signal includes second information contained within the first signal.
11. The apparatus of claim 9 , wherein:
the first signal has a first frequency;
the second signal has a second frequency; and
the third signal has the second frequency.
12. The apparatus of claim 9 , wherein:
the first signal has a first frequency;
the second signal has a second frequency;
the third signal has the second frequency; and
the first frequency is greater than the second frequency.
13. The apparatus of claim 9 , wherein:
the first signal has a first frequency;
the second signal has a second frequency;
the third signal has the second frequency;
the fourth signal has the second frequency;
the fifth signal has the second frequency; and
the first frequency is greater than the second frequency.
14. The apparatus of claim 9 , wherein:
the first circuit block, the second circuit block, and the third circuit block are all implemented on a single silicon die.
15. An apparatus, comprising:
a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a first signal thereby generating a second signal and a third signal there from;
a second circuit block, implemented using conventional complementary metal-oxide semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process the second signal thereby generating a fourth signal there from;
a third circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the third signal thereby generating a fifth signal there from.
a fourth circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to:
receive the fourth signal;
receive the fifth signal; and
process the fourth signal and the fifth signal thereby generating a sixth signal there from.
16. The apparatus of claim 15 wherein:
the first circuit block deserializes the first signal thereby generating the second signal and the third signal there from such that the second signal includes first information contained within the first signal and the third signal includes second information contained within the first signal.
17. The apparatus of claim 15 , wherein:
the fourth circuit block serializes the fourth signal and the fifth signal thereby generating the sixth signal such that the sixth signal includes information contained within the fourth signal and the fifth signal.
18. The apparatus of claim 15 , wherein:
the first signal has a first frequency;
the second signal has a second frequency;
the fourth signal has the second frequency; and
the sixth signal has the first frequency.
19. The apparatus of claim 15 , wherein:
the first signal has a first frequency;
the second signal has a second frequency;
the third signal has the second frequency;
the fourth signal has the second frequency;
the fifth signal has the second frequency; and
the sixth signal has the first frequency.
20. The apparatus of claim 15 , wherein:
the first circuit block, the second circuit block, the third circuit block, and the fourth circuit block are all implemented on a single silicon die.