Granted Patent B1

US 7,107,202 · App. 09/495,150 · Granted Sep 12, 2006

Abstract

Claims (26)

1. A method of developing an ASIC comprising:

developing a hardware model including a CPU bus functional model, and a software loaded on a CPU server concurrently;

communicating command and control information between the CPU server and the CPU bus functional model over a network according to an XBUS protocol modified to exchange data for all modules using the XBUS protocol by sharing a plurality of registers and without using a physical bus;

co-simulating the hardware model and the software; and

receiving real working environment test inputs for the co-simulation.

2. The method of claim 1 , wherein the hardware model is developed on a workstation.

3. The method of claim 1 , wherein the software is developed on a target board.

4. The method of claim 1 , wherein the co-simulated hardware model is described by a high-level language model.

5. A method of co-simulating a hardware model and a software in ASIC development, comprising:

Requesting, by a hardware side including a hardware model and a CPU bus functional model, access to a software side including a software loaded on CPU server over a network according to a modified XBUS protocol to exchange data for all modules using the XBUS protocol by sharing a plurality of resisters and without using a physical bus;

invoking a function call by the CPU server;

sending an access request from the CPU bus functional model to the CPU server over the network according to the modified XBUS protocol;

routing the access request to the hardware model;

co-simulating the hardware model and the software; and

receiving real working environment test inputs for the co-simulation.

6. The method of claim 5 , wherein the function call is a READ function call.

7. The method of claim 5 , wherein the function call is a WRITE function call.

8. The method of claim 5 , further comprising:

requesting a hardware model interrupt; and

handling the hardware model interrupt with a function call invoked by the CPU server over the network.

9. An apparatus for hardware model and software co-simulation in ASIC development, comprising:

a hardware model including a CPU bus functional model to represent a hardware board circuit;

a software to load on a CPU server to provide command and control access of the hardware model;

a network coupled to the CPU bus functional model and the CPU server to communicate a command from the software to the hardware model and to route contents of the command between the hardware model and software according to a modified XBUS protocol to exchange data without using a physical bus to provide co-simulation of the hardware model and software; and

a plurality of shared registers coupled to the hardware model and the software, the shared registers configured to communicate according to the modified XBUS protocol

wherein the hardware model is configure to receive real working environment test inputs for the co-simulation.

Assignments (8)