Patent Assignment
Reel/Frame 030747/0001
Assignment of Assignor's Interest
Recorded: 2013-07-04
Pages: 126
Assignor
INTEL CORPORATION
Executed: 2011-11-22
Assignee
MICRON TECHNOLOGY, INC.
8000 SO. FEDERAL WAY, BOISE, IDAHO, 83716-9632
Covered Properties
(500)
Method for the Anisotropic Etching of Metal Films in the Fabrication of Interconnects
Patent:
5,350,484 →
Application:
07/941,412 →
Programmable Secondary Clock Generator
Patent:
5,256,994 →
Application:
07/948,215 →
Polishing Pad Conditioning Apparatus for Wafer Planarization Process
Patent:
5,216,843 →
Application:
07/950,812 →
Improved System of Resolving Conflicting Data Processing Memory Requests
Patent:
5,339,442 →
Application:
07/954,743 →
System for Automatically Compressing and Decompressing Data for Sender and Reciever Processes Upon Determination of a Common Compression/ Decompression Method Understood by Both Sender and Reciever Processes
Patent:
5,557,749 →
Application:
07/961,475 →
Method for Controlling Dataflow Between a Plurality of Circular Buffers
Patent:
5,446,839 →
Application:
08/067,858 →
Method and Apparatus for Providing a Context Switch in Response to an Interrupt in a Computer Process
Patent:
5,535,397 →
Application:
08/085,409 →
Method and Apparatus for Providing Precise Fault Tracing in a Superscalar Microprocessor
Patent:
5,752,013 →
Application:
08/085,508 →
Special Test Modes for a Page Buffer Shared Resource in a Memory Device
Patent:
5,623,620 →
Application:
08/085,542 →
Method and Apparatus for Controlling the Output Current Provided by a Charge Pump Circuit
Patent:
5,442,586 →
Application:
08/119,425 →
Circuit and Method for Digital to Analog Signal Conversion
Patent:
5,469,164 →
Application:
08/129,899 →
Generally-Diagonal Mapping of Address Space for Row/Column Organizer Memories
Patent:
5,490,264 →
Application:
08/130,023 →
Novel Slurries for Chemical Mechanical Polishing
Patent:
5,340,370 →
Application:
08/146,923 →
Analog Chroma Keying on Color Data
Patent:
5,398,075 →
Application:
08/154,955 →
Fast Parity Generator Using Complement Pass-Transistor Logic
Patent:
5,608,741 →
Application:
08/156,427 →
Cmos Voltage Reference Circuit
Patent:
5,434,534 →
Application:
08/158,418 →
Tab Tape
Patent:
5,473,190 →
Application:
08/167,531 →
Parallel Multistage Synchronization Method and Apparatus
Patent:
5,488,639 →
Application:
08/171,554 →
Critical Path Prediction for Design of Circuits
Patent:
5,544,071 →
Application:
08/174,729 →
Method and Circuitry for Enabling and Permanently Disabling Test Mode Access in a Flash Memory Device
Patent:
5,526,311 →
Application:
08/175,599 →
Method and Apparatus for Assigning Memory Space Addresses to Memory on Computer Interface Boards
Patent:
5,745,786 →
Application:
08/188,555 →
Architecture and Method for Providing Guaranteed Access for a Retrying Bus Master to a Data Transfer Bridge Connecting Two Buses in a Computer System
Patent:
6,026,455 →
Application:
08/201,817 →
An Electronic Package That Has a Die Coupled to a Lead Frame by a Dielectric Tape and a Heat Sink That Provides Both an Electrical and a Thermal Path Between the Die and the Lead Frame
Patent:
5,444,602 →
Application:
08/201,895 →
Single Stage Sensing Apparatus for a Content Addressable Memory
Patent:
5,428,565 →
Application:
08/212,350 →
Low Impact Collision Detection Method
Patent:
5,463,658 →
Application:
08/216,668 →
Ring Tone Detection for a Telephone System
Patent:
5,442,694 →
Application:
08/226,678 →
Process, Apparatus and System for Transforming Signals Using Pseudo-Simd Processing
Patent:
5,559,722 →
Application:
08/234,976 →
Process, Apparatus and System for Selecting Quantization Levels for Encoding Video Signals
Patent:
5,532,940 →
Application:
08/234,978 →
Binmos Driver Circuit with Integrated Voltage Supply Conversion
Patent:
5,436,585 →
Application:
08/242,790 →
Cache Memory Utilizing Pseudo-Static Four Transistor Memory Cell
Patent:
5,475,633 →
Application:
08/252,320 →
Drain Bias Multiplexing for Multiple Bit Flash Cell
Patent:
5,485,422 →
Application:
08/252,684 →
Synchronous Address Latching for Memory Arrays
Patent:
5,497,355 →
Application:
08/253,842 →
Bit Map Addressing Schemes for Flash Memory
Patent:
5,497,354 →
Application:
08/253,902 →
Low Capacitance Content-Addressable Memory Cell
Patent:
5,490,102 →
Application:
08/260,044 →
Parallel Flexible Transmission Cable
Patent:
5,557,075 →
Application:
08/266,150 →
Method and Apparatus for Preventing Over-Erasure of Flash Eeprom Memory Devices
Patent:
5,490,109 →
Application:
08/267,472 →
Displaying Caller Identification Information in a Computer System
Patent:
5,546,447 →
Application:
08/268,265 →
I/O Connector for Add in Printed Circuit Cards for Computer Systems
Patent:
5,477,418 →
Application:
08/275,599 →
Method and Apparatus for Routing in Reduced Switch Matrices to Provide One Hundred Percent Coverage
Patent:
5,572,198 →
Application:
08/279,954 →
Method of Adapting Processing Parameters in a Call Processing System
Patent:
5,506,885 →
Application:
08/289,315 →
Rendering an Inter Versus Intra Video Encoding Decision Based Upon a Vertical Gradient Measure of Target Video Frames
Patent:
5,600,375 →
Application:
08/302,595 →
Throttling Circuit for a Data Transfer System
Patent:
5,434,892 →
Application:
08/307,502 →
Test Flow Assurance Using Memory Imprinting
Patent:
5,538,141 →
Application:
08/312,831 →
Programmable High Watermark in Stack Frame Cache Using Second Region as a Storage If First Region Is Full and an Event Having a Predetermined Minimum Priority
Patent:
5,636,362 →
Application:
08/314,418 →
Dual Row Selection Using Multiplexed Tri-Level Decoder
Patent:
5,517,138 →
Application:
08/316,546 →
Call Processing Using Previously Obtained Line Characteristics
Patent:
5,764,759 →
Application:
08/319,159 →
Encoding Video Signals Using Local Quantization Levels
Patent:
5,802,213 →
Application:
08/324,923 →
Power Validation Tool for Microprocessor Systems
Patent:
5,525,913 →
Application:
08/325,879 →
Low Power Voltage Detector Circuit Including a Flash Memory Cell
Patent:
5,495,453 →
Application:
08/326,689 →
Decoding Variable-Length Encoded Signals
Patent:
5,589,829 →
Application:
08/329,340 →
Run-Length Encoding Sequence for Video Signals
Patent:
5,552,832 →
Application:
08/329,524 →
Encoding Video Signals Using Selective Pre-Filtering
Patent:
5,557,330 →
Application:
08/332,583 →
Hi-Jack Hinged Connection Adapter for Input/Output Cards
Patent:
5,637,018 →
Application:
08/333,139 →
Method and Apparatus for Endpoint Detection in a Chemical/Mechanical Process for Polishing a Substrate
Patent:
5,595,526 →
Application:
08/347,813 →
Smart Battery Providing Battery Life and Recharge Time Prediction
Patent:
5,565,759 →
Application:
08/356,905 →
Low Load Host/Pci Bus Bridge
Patent:
5,740,385 →
Application:
08/358,359 →
Error Management Processes for Flash Eeprom Memory Arrays
Patent:
5,475,693 →
Application:
08/364,546 →
Clocking Scheme for Latching of a Domino Output
Patent:
5,453,708 →
Application:
08/368,335 →
Method and Apparatus for Compensating for Subthreshold Current in a Static Ram
Patent:
5,517,452 →
Application:
08/403,407 →
Four Wire Modem Signal Switching for Voice and Data Applications
Patent:
5,602,902 →
Application:
08/410,212 →
Algorithmic Array Mapping to Decrease Defect Sensitivity of Memory Devices
Patent:
5,943,693 →
Application:
08/412,555 →
Apparatus and Method for Selecting a Tap Range in a Digital Delay Line
Patent:
5,537,069 →
Application:
08/413,951 →
Use of Rssi Indication for Improved Data Transmission Over Amps Network
Patent:
5,612,991 →
Application:
08/414,914 →
Method and Apparatus for Cooperative Messaging
Patent:
5,621,798 →
Application:
08/423,306 →
A Branch Predictor Using Multiple Prediction Heuristics and a Heuristic Identifier in the Branch Instruction
Patent:
5,687,360 →
Application:
08/431,016 →
Memory Unit with Bit Line Discharger
Patent:
5,627,788 →
Application:
08/437,090 →
Power Supply Configured Sensing Scheme for Flash Eeprom
Patent:
5,572,465 →
Application:
08/451,037 →
Method and Apparatus for Improving Power Up Time of Flash Eeprom Memory Arrays
Patent:
5,640,083 →
Application:
08/458,805 →
Photolithography Method Using Coherence Distance Control
Patent:
5,801,821 →
Application:
08/497,321 →
Low Power Programmable Logic Arrays
Patent:
5,576,636 →
Application:
08/515,248 →
Instruction Dependency Chain Indentifier
Patent:
5,710,902 →
Application:
08/524,065 →
Method and Apparatus to Improve Latency Experienced by an Agent Under a Round Robin Arbitration Scheme
Patent:
5,640,519 →
Application:
08/528,914 →
Method and Apparatus for Accommodating Different Issue Width Implementations of Vliw Architectures
Patent:
5,848,288 →
Application:
08/530,076 →
Multiplexer Having a Plurality of Internal Data Paths That Operate at Different Speeds
Patent:
5,625,303 →
Application:
08/534,485 →
Methods and Apparatus for Correlating Stuck-at Fault Test Coverage and Current Leakage Fault Test Coverage
Patent:
5,712,857 →
Application:
08/536,112 →
Circuit for Detecting When a Supply Output Voltage Exceeds a Predetermined Level
Patent:
5,602,502 →
Application:
08/536,853 →
Fast Floating-Point to Integer Conversion
Patent:
5,764,548 →
Application:
08/537,260 →
Telephone Call Setup Procedure
Patent:
6,377,576 →
Application:
08/541,678 →
System and Method for Programming Programmable Electronic Components Using Board-Level Automated Test Equipment
Patent:
5,794,007 →
Application:
08/553,017 →
No Handle Zip Socket
Patent:
5,602,719 →
Application:
08/558,032 →
Locking Power Cable Interface Guard
Patent:
5,735,701 →
Application:
08/570,239 →
Method and Apparatus for Testing a Memory Where Data Is Passed Through the Memory for Comparison with Date Read from the Memory
Patent:
5,592,425 →
Application:
08/576,705 →
Reorder Buffer with Inerleaving Mechanism for Accessing a Multi-Porter Circular Memory Array
Patent:
5,787,454 →
Application:
08/578,964 →
Multiple Intake Duct Microprocessor Cooling System
Patent:
5,691,883 →
Application:
08/578,984 →
Pla Architecture Having Improved Clock Signal to Output Timing Using a Type-I Domino and Plane
Patent:
5,712,578 →
Application:
08/579,095 →
Method and Apparatus for Eliminating Visual Artifacts Caused by Diffusing Errors in a Decimated Video Signal
Patent:
5,777,624 →
Application:
08/582,200 →
Connector with Attachable Daughter Card Retention System
Patent:
5,784,263 →
Application:
08/584,330 →
Telephone Network with Normally Off Hook Telephones
Patent:
5,912,950 →
Application:
08/594,016 →
Use of Caller Id Information
Patent:
5,787,159 →
Application:
08/607,796 →
Table-Driven Bi-Directional Motion Estimation Using Scratch Area and Offset Values
Patent:
5,778,097 →
Application:
08/610,582 →
Cleaning Step Which Improves Electromigration Performance of Interlayer Connection in Integrated Circuits
Patent:
5,904,560 →
Application:
08/623,672 →
Anchor Provisions to Prevent Mold Delamination in an Overmolded Plastic Array Package
Patent:
5,773,895 →
Application:
08/627,058 →
Random Number Generator
Patent:
5,706,218 →
Application:
08/648,553 →
Circuit Board Retention System
Patent:
5,726,865 →
Application:
08/665,405 →
Apparatus and Method for Controlling the Temperature of an Integrated Circuit Under Test
Patent:
5,847,366 →
Application:
08/668,045 →
Apparatus for Protecting Gate Electrodes of Target Transisitors in the Gate Array from Gate Charging by Employing Free Transistors in the Gate Array
Patent:
5,793,069 →
Application:
08/672,411 →
Slow Speed Driver with Controlled Slew Rate
Patent:
5,757,217 →
Application:
08/672,412 →
Multivoltage Keyed Electrical Connector
Patent:
6,080,022 →
Application:
08/672,643 →
Apparatus and Method for Computation of Sticky Bit in a Multi-Stage Shifter Used for Floating Point Arithmetic
Patent:
5,771,183 →
Application:
08/672,678 →
Cladding of an Interconnect for Improved Electromigration Performance
Patent:
5,909,635 →
Application:
08/673,277 →
Method for Extracting a Resistor Network from an Integrated Circuit Polygon Layout
Patent:
5,943,487 →
Application:
08/679,197 →
Comparator Utilizing Redundancy
Patent:
5,881,076 →
Application:
08/682,108 →
Method and Apparatus for Guided Touring of Internet/Intranet Websites
Patent:
5,809,247 →
Application:
08/685,952 →
Method for Verifying Contiguity of a Binary Translated Block of Instructions by Attaching a Compare and/or Branch Instruction to Predecessor Block of Instructions
Patent:
5,721,927 →
Application:
08/689,357 →
Circuit Board Retention System
Patent:
5,642,263 →
Application:
08/689,698 →
Latching Mechanism for Pulsed Domino Logic with Inherent Race Margin and Time Borrowing
Patent:
5,796,282 →
Application:
08/700,613 →
Method and Apparatus for the Non-Invasive Testing of Printed Circuit Board Assemblies
Patent:
5,802,074 →
Application:
08/715,857 →
Organic Substrate (Pcb) Slip Plane "Stress Deflector" for Flip Chip Devices
Patent:
5,804,771 →
Application:
08/721,268 →
System and Method for Ensuring Integrity of Audio
Patent:
5,946,396 →
Application:
08/738,086 →
Process for Forming an Integrated Structure Comprising a Self-Aligned via/Contact and Interconnect
Patent:
5,888,897 →
Application:
08/739,879 →
Key Management System for Dvd Copyright Management
Patent:
5,915,018 →
Application:
08/740,976 →
Method and Apparatus for Facilitating Detection of Solder Opens of Smt Components
Patent:
5,966,020 →
Application:
08/741,053 →
Data Speculatable Processor Having Replay Architecture
Patent:
5,966,544 →
Application:
08/746,547 →
Method and Apparatus for Controlling a Charge Pump for Rapid Initialization
Patent:
5,880,622 →
Application:
08/768,297 →
Method and Apparatus for Tracking Erase Cycles Utilizing Active and Inactive Wear Bar Blocks Having First and Second Count Fields
Patent:
5,963,970 →
Application:
08/770,958 →
Method and Apparatus for Distribution of Broadcast Data
Patent:
5,889,950 →
Application:
08/771,709 →
An Out-of-Order Superscalar Microprocessor with a Renaming Device That Maps Instructions from Memory to Registers
Patent:
5,838,941 →
Application:
08/774,659 →
Method of Producing a Ceramic Package Main Body
Patent:
5,822,851 →
Application:
08/775,305 →
Etch Process to Produce Rounded Top Corners for Sub Micron Silicon Trench Applications
Patent:
5,843,846 →
Application:
08/775,573 →
Method and Apparatus for Converting a Five Wire Arbitration/Buffer Management Protocol into a Two Wire Protocol
Patent:
5,918,025 →
Application:
08/775,807 →
Method and Apparatus for Mounting a Very Large Scale Integration (Vlsi) Chip to a Computer Chassis for Cooling
Patent:
5,978,228 →
Application:
08/777,604 →
Appratus for Performing a User Requested Reset During Algorithm Execution
Patent:
6,055,614 →
Application:
08/778,015 →
Method and Apparatus for Connecting Expansion Buses to a Peripheral Component Interconnect Bus
Patent:
5,951,667 →
Application:
08/778,192 →
Method and Apparatus for Dynamic Location and Control of Processor Resources to Increase Resolution of Data Dependency Stalls
Patent:
5,918,033 →
Application:
08/780,675 →
Method for Calibrating a Digital Camera to a Pc Monitor to Enhance Picture Quality of a Picture Captured by the Digital Camera and Displayed on the Pc Monitor
Patent:
5,918,192 →
Application:
08/787,865 →
Method and Apparatus for Delivering Data
Patent:
5,987,504 →
Application:
08/801,508 →
Spread Spectrum Codes for Use in Communication
Patent:
6,282,228 →
Application:
08/821,611 →
Packaging Multiple Dies on a Ball Grid Array Substrate
Patent:
5,815,372 →
Application:
08/822,743 →
Method and Apparatus for Determining Digits Dialed Using a Selected Algorithm
Patent:
5,881,146 →
Application:
08/828,000 →
Employing a Look-Up Service and a Callee Connection Service to Establish a Network Phone Call Between a Caller and a Callee
Patent:
6,192,044 →
Application:
08/829,608 →
Method for Performing Common Subexpression Elimination on a Rack-N Static Single Assignment Language
Patent:
6,002,879 →
Application:
08/829,856 →
Method for Using Static Single Assignment to Color Out Artificial Register Dependencies
Patent:
6,016,398 →
Application:
08/831,739 →
Self-Containing Input Buffer on Flash Memories
Patent:
6,628,552 →
Application:
08/834,029 →
Self-Configuring Output Buffer on Flash Memories
Patent:
5,903,500 →
Application:
08/834,032 →
Dynamically Controlling the Number of Boundary-Scan Cells in a Boundary-Scan Path
Patent:
5,768,289 →
Application:
08/862,006 →
Method and Apparatus for Automatically Determining and Dynamically Updating User Preferences in an Entertainment System
Patent:
5,945,988 →
Application:
08/866,707 →
Variable Loading Apparatus for Output Loading of Integrated Circuits
Patent:
5,900,770 →
Application:
08/874,496 →
Scalable Receiver Structure for Efficient Bit Sequence Decoding
Patent:
6,069,928 →
Application:
08/885,803 →
Anti-Theft Mechanism for Mobile Computers
Patent:
6,151,678 →
Application:
08/927,370 →
A Sense Amplifier Comprising a Preamplifier and a Differential Input Latch for Flash Memories
Patent:
5,973,957 →
Application:
08/931,247 →
Computer Package with a Polygonal Shaped Motherboard
Patent:
5,903,432 →
Application:
08/933,405 →
Method and Apparatus for Using Function Context to Improve Branch Prediction
Patent:
5,964,870 →
Application:
08/934,964 →
Computer System Including Right Angle Processor and Add-on Card Connectors
Patent:
5,978,873 →
Application:
08/936,857 →
Method and Apparatus Employing a Dynamic Encryption Interface Between a Processor and a Memory
Patent:
5,987,572 →
Application:
08/937,874 →
Circuit and Method for Configuring and Registering a Cryptographic Device
Patent:
5,970,147 →
Application:
08/938,491 →
Merging Dummy Structure Representations for Improved Distribution of Artifacts in a Semiconductor Layer
Patent:
6,081,272 →
Application:
08/941,599 →
System for Speculative Branch Target Predicition Having a Dynamic Predicition History Buffer and a Static Prediction History Buffer
Patent:
5,978,909 →
Application:
08/979,579 →
Quad Flat Pack Integrated Circuit Package
Patent:
5,867,367 →
Application:
08/984,766 →
Method and Apparatus of Resolving a Deadlock by Collapsing Writebacks to a Memory
Patent:
6,134,635 →
Application:
08/987,279 →
Thermal Interface Attach Mechanism for Electrical Packages
Patent:
5,965,937 →
Application:
08/990,856 →
Branch Instruction Handling in a Self-Timed Marking System
Patent:
5,931,944 →
Application:
08/996,756 →
Efficient Self-Timed Marking of Lengthy Variable Length Instructions
Patent:
5,941,982 →
Application:
08/997,461 →
Pickup Chuck with an Integral Heatsink
Patent:
6,019,166 →
Application:
09/000,981 →
Hot Shear Apparatus and Method for Removing a Semiconductor Chip from an Existing Package
Patent:
6,029,730 →
Application:
09/001,021 →
Supplying Standby Voltage to Memory and Wakeup Circuitry to Wake a Computer from a Low Power Mode
Patent:
6,308,278 →
Application:
09/001,102 →
Unique Chemical Mechanical Planarization Approach Which Utilizes Magnetic Slurry for Polish and Magnetic Fields for Process Control
Patent:
6,083,839 →
Application:
09/001,509 →
Static, High-Sensitivity, Fuse-Based Storage Cell
Patent:
5,959,445 →
Application:
09/002,174 →
Automatic Transfer of Image Information Between Imaging Device and Host System
Patent:
6,256,059 →
Application:
09/003,732 →
A Charge Pump Avoiding Gain Degradation Due to the Body Effect
Patent:
6,232,826 →
Application:
09/005,560 →
Method and Apparatus for Finding Loop_Lever Parallelism in a Pointer Based Application
Patent:
6,272,676 →
Application:
09/006,276 →
Low Voltage Programmable Complementary Input Stage Sense Amplifier
Patent:
6,051,999 →
Application:
09/006,770 →
High Speed Analog Compensated Input Buffer
Patent:
6,144,218 →
Application:
09/012,201 →
Bus Protocol for Atomic Transactions
Patent:
5,987,552 →
Application:
09/013,774 →
Fan Duct Module
Patent:
6,130,819 →
Application:
09/015,423 →
Overlay Counter for Accelerated Graphics Port
Patent:
6,199,149 →
Application:
09/016,790 →
Plga Test Handler Throw Measuring Unit
Patent:
5,948,960 →
Application:
09/020,661 →
Electronic Cartridge Which Allows Differential Thermal Expansion Between Components of the Cartridge
Patent:
5,894,408 →
Application:
09/024,860 →
Intergrated Processor Substrate Protective Enclosure for Use in Desktop Pc Systems
Patent:
6,084,773 →
Application:
09/024,921 →
Memory Test Mode for Wordline Resistive Defects
Patent:
6,085,341 →
Application:
09/030,522 →
Pump Supply Self Regulation for Flash Memory Cell Pair Reference Circuit
Patent:
5,946,258 →
Application:
09/040,523 →
Codee with Genetic Adaptation
Patent:
6,539,366 →
Application:
09/071,049 →
Fan Duct Module
Patent:
6,064,571 →
Application:
09/074,951 →
Bypassable Amplifier
Patent:
6,137,354 →
Application:
09/080,812 →
Parallel Access Testing of a Memory Array
Patent:
5,982,684 →
Application:
09/086,330 →
Silicon Wafer Testing Rig and a Method for Testing a Silicon Wafer Wherein the Silicon Wafer Is Bent into a Dome Shape
Patent:
6,100,709 →
Application:
09/087,753 →
Retention Mechanism Assembly for Processor Cartridges with Captured Screw Fasteners
Patent:
6,208,527 →
Application:
09/098,086 →
Method and Device for Quantizing the Input to Soft Decoders
Patent:
6,047,035 →
Application:
09/103,683 →
Cart for Transferring Objects
Patent:
6,102,647 →
Application:
09/105,191 →
Method and Apparatus for Updating a Timer from Multiple Timing Domains
Patent:
6,021,505 →
Application:
09/105,479 →
Computer Processor with a Replay System
Patent:
6,163,838 →
Application:
09/106,857 →
Thin Oxides of Silicon
Patent:
6,221,789 →
Application:
09/124,562 →
Selecting Design Points on Parameter Functions Having First Sum of Constraint Set and Second Sum of Optimizing Set to Improve Second Sum Within Design Constraints
Implementing Micro Bga Assembly Techniques for Small Die
Patent:
6,655,022 →
Application:
09/160,535 →
Charge Controlled Mirror with Improved Frame Time Utilization and Method of Addressing the Same
Patent:
6,028,696 →
Application:
09/172,615 →
Beam-Addressed Micromirror Direct View Display
Patent:
6,031,656 →
Application:
09/179,933 →
Method and Apparatus for Controlling a Computer to Implement Telephone Functions with a Displayed Telephone of Variable Size
Patent:
6,240,168 →
Application:
09/182,828 →
Color Interpolation for a Four Color Mosaic Pattern
Patent:
6,759,646 →
Application:
09/199,836 →
Chemical-Mechanical Polishing Slurry
Patent:
6,077,337 →
Application:
09/203,432 →
Dtmf Detection in Internet Telephony
Patent:
6,400,709 →
Application:
09/204,607 →
Advanced Near Ideal Mixer
Patent:
6,184,739 →
Application:
09/205,992 →
Membrane-Actuated Charge Controlled Mirror (Ccm) Projection Display
Patent:
6,031,657 →
Application:
09/208,041 →
Cyclic Multicasting or Asynchronous Broadcasting of Computer Files
Patent:
6,256,673 →
Application:
09/213,220 →
Tactile Tracking Systems and Methods
Patent:
6,515,586 →
Application:
09/216,580 →
System and Method for Automatically Identifying and Attaching Related Documents
Quantum Magnetic Memory
Patent:
6,061,265 →
Application:
09/221,233 →
Hot Plug Structure and Method for Engaging/Disengaging Pci Compliant Card
Patent:
6,162,073 →
Application:
09/223,811 →
Memory Card Which Is Thermally Controlled
Patent:
6,163,474 →
Application:
09/225,927 →
Data-Flow Method of Analyzing Definitions and Uses of L Values in Programs
Patent:
6,370,685 →
Application:
09/226,804 →
Universal Pulse Synchronizer
Patent:
6,172,538 →
Application:
09/226,924 →
Signal Transition Detector for Asynchronous Circuits
Patent:
6,075,751 →
Application:
09/231,725 →
System and Method for Controlling an Electronic Device
Patent:
7,342,612 →
Application:
09/250,940 →
Hmgi(Y)-LAMA4* Fusion Oncogene, Oncoprotein and Methods of Use
Patent:
6,150,110 →
Application:
09/258,373 →
Neural-Flash Analog-to-Digital Converter Using Weighted Current Similation
Patent:
6,198,421 →
Application:
09/259,650 →
Two-Dimensional Queuing/De-Queuing Methods and Systems for Implementing the Same
Patent:
6,724,767 →
Application:
09/271,061 →
Method and Apparatus for the Generation of Statistically Random Numbers
Patent:
6,374,278 →
Application:
09/276,366 →
Computer Telephony Server with Improved Flexibility
Patent:
7,123,712 →
Application:
09/277,286 →
Test Fixture for Testing a Multi-Port Voice Processing Card and the Like
Patent:
6,595,798 →
Application:
09/280,171 →
Method for Motion Compensated Frame Rate Upsampling Based on Piecewise Affine Warping
Patent:
6,438,275 →
Application:
09/296,451 →
Method and Apparatus for Dual Mode Output Buffer Impedance Compensation
Patent:
6,166,563 →
Application:
09/299,771 →
Dynamic and Scheduled Computer Telephony Resource Allocation
Patent:
6,643,367 →
Application:
09/301,855 →
Method and Apparatus for Providing Redundancy in Non-Volatile Memory Devices
Patent:
6,072,723 →
Application:
09/306,322 →
High-Speed Digital Distribution System
Patent:
6,449,308 →
Application:
09/318,287 →
Method for Direscting the Route of a Cell Transmitting a Network
Patent:
6,654,369 →
Application:
09/322,152 →
Ray Intersection Reduction Using Directionally Classified Target Lists
Patent:
6,489,955 →
Application:
09/327,015 →
Application Programming Interfaces and Methods Enabling a Host to Interface with a Network Processor
Patent:
6,604,136 →
Application:
09/337,025 →
System for Multi-Layer Broadband Provisioning in Computer Networks
Systems and Methods for Implementing Pointer Management
Patent:
6,425,067 →
Application:
09/340,282 →
Flip-Flop Circuit
Patent:
6,181,180 →
Application:
09/340,417 →
System and Method for Performing Cut-Through Forwarding in an Atm Network Supporting Lan Emulation
Multi-Protocol Conversion Assistance Method and System for a Network Accelerator
Patent:
6,603,768 →
Application:
09/344,672 →
Charge Pump with Gated Pumped Output Diode at Intermediate Stage
Patent:
6,151,229 →
Application:
09/346,483 →
Setting the Common Mode Level of a Differential Charge Pump Output
Patent:
6,184,732 →
Application:
09/370,622 →
Apparatus for Fast Logic Transfer of Data Across Asynchronous Clock Domains
Patent:
6,172,540 →
Application:
09/374,798 →
Stochastic Sampling with Constant Density in Object Space for Anisotropic Texture Mapping
Patent:
6,400,370 →
Application:
09/393,477 →
Method and Apparatus for Interlaced Image Enhancement
Patent:
6,384,872 →
Application:
09/395,000 →
Magnetic Ink Encoding Pen
Patent:
7,197,174 →
Application:
09/396,407 →
Method and Apparatus for Rapid Initialization of Charge Pump Circuits
Patent:
6,255,896 →
Application:
09/406,329 →
Method and Apparatus for Transferring Wafer Cassettes in Microelectronic Manufacturing Environment
Patent:
6,364,331 →
Application:
09/410,400 →
Method of Compressing a Color Image
Patent:
6,798,901 →
Application:
09/411,697 →
Elastic Buffer
Patent:
6,594,329 →
Application:
09/432,050 →
Method and Apparatus for Adaptive Hierarchical Visibility in a Tiled Three-Dimensional Graphics Architecture
Patent:
6,525,726 →
Application:
09/432,134 →
Self-Tuning Amplifier
Patent:
6,268,774 →
Application:
09/434,250 →
Gate Enhancement Charge Pump for Low Voltage Power Supply
Patent:
6,292,048 →
Application:
09/438,186 →
Pixel Span Depth Buffer
Up-Sampling Decimated Color Plane Data
Patent:
6,580,837 →
Application:
09/457,058 →
Hash Cam Having a Reduced Width Comparison Circuitry and Its Application
Method and Apparatus for Maintaining Order in a Pipelined Process and Its Application
Patent:
6,754,764 →
Application:
09/468,965 →
Multi-Link Extensions and Bundle Skew Management
Patent:
6,646,991 →
Application:
09/470,189 →
Method and Apparatus for Switching an Optical Beam
Patent:
6,650,802 →
Application:
09/470,574 →
Method and Apparatus for Performing Distributed Simulation Utilizing a Simulation Backplane
Patent:
7,319,947 →
Application:
09/470,875 →
Optical Fiber Coating Compositions Containing Secondary or Tertiary Amino Silicone-Containing Additive
Patent:
6,538,045 →
Application:
09/471,694 →
Technique for Synchronizing Faults in a Processor Having a Replay System
Patent:
6,629,271 →
Application:
09/472,839 →
Field Frame Motion Design for Digital Video Decoder
Patent:
6,560,286 →
Application:
09/474,183 →
Voltage Tolerant High Drive Pull-Up Driver for an I/O Buffer
Patent:
6,388,475 →
Application:
09/474,566 →
Partial Underfill for Flip-Chip Electronic Packages
Patent:
6,700,209 →
Application:
09/474,746 →
Shifting an Input Signal from a High-Speed Domain to a Lower-Speed Domain
Patent:
6,668,298 →
Application:
09/474,750 →
Interface to a Memory System for a Processor Having a Replay System
Patent:
6,665,792 →
Application:
09/475,029 →
Voltage Blocking Method and Apparatus for a Charge Pump with Diode Connected Pull-Up and Pull-Down on Boot Nodes
Method and Apparatus for Hardware and Software Co-Simulation
Patent:
7,107,202 →
Application:
09/495,150 →
Method of Inverse Quantized Signal Samples of an Image During Image Decompression
Patent:
6,961,472 →
Application:
09/507,213 →
Method of Quantizing Signal Samples of an Image During Same
Patent:
6,748,118 →
Application:
09/507,399 →
Multiple Platform Voice Processing System with Optimized Resource Allocation
Patent:
6,418,201 →
Application:
09/510,311 →
Process for Forming Microelectronic Packages and Intermediate Structures Formed Therewith
Patent:
6,586,836 →
Application:
09/516,652 →
Method of Processing an Inbound Call in a Call Center
Patent:
6,975,720 →
Application:
09/523,935 →
Trimming Surfaces
Patent:
7,180,523 →
Application:
09/539,343 →
Shared Credit Round Robin Queuing
Patent:
6,683,884 →
Application:
09/541,048 →
Data-Flow Method for Optimizing Exception-Handling Instructions in Programs
Patent:
7,120,904 →
Application:
09/552,292 →
Multi-Wireless Network Configurable Behavior
Patent:
7,193,965 →
Application:
09/565,215 →
Pad and Codec Detection
Patent:
6,724,814 →
Application:
09/598,934 →
Device to Receive, Buffer, and Transmit Packets of Data in a Packet Switching Network
Patent:
6,778,548 →
Application:
09/603,957 →
Method and Apparatus for Providing a Secure-Private Partition on a Hard Disk Drive of a Computer System via Ide Controller
Patent:
7,155,615 →
Application:
09/608,117 →
User Transparent Continuous Compilation
Patent:
7,240,342 →
Application:
09/608,616 →
Methods and Apparatus for Fast Argument Reduction in a Computing System
Patent:
7,366,748 →
Application:
09/609,496 →
Plasma Induced Depletion of Fluorine from Surfaces of Fluorinated Low-K Dielectric Materials
Patent:
6,846,737 →
Application:
09/639,625 →
Method and Apparatus to Improve the Protection of Information Presented by a Computer
Patent:
7,007,304 →
Application:
09/665,826 →
Method and Apparatus for a Low Latency Source-Synchronous Address Receiver for a Host System Bus in a Memory Controller
Patent:
6,748,513 →
Application:
09/665,922 →
Runtime Prediction Framework for Cpu Intensive Applications
Patent:
7,168,074 →
Application:
09/675,286 →
Executing a Translated Block of Instructions and Branching to Correction Code When Expected Top of Stack Does Not Match Actual Top of Stack to Adjust Stack at Execution Time to Continue Executing Without Restarting Translating
Patent:
7,340,592 →
Application:
09/676,175 →
Clock splitter circuit to generate synchronized clock and inverted clock
Patent:
6,384,658 →
Application:
09/676,313 →
Efficient Implementation of N-Point Dct, N-Point Idct, Sa-Dct and Sa-Idct Algorithms
Patent:
7,216,140 →
Application:
09/676,556 →
Post Etch Clean Sequence for Making a Semiconductor Device
Patent:
6,465,358 →
Application:
09/684,550 →
I/O Device Testing Method and Apparatus
Patent:
6,671,847 →
Application:
09/709,000 →
Method for Switching Data Streams
Patent:
6,842,452 →
Application:
09/712,185 →
Code-Switched Optical Networks
Patent:
6,865,344 →
Application:
09/712,822 →
Interconnect Mechanics for Electromagnetic Coupler
Patent:
6,498,305 →
Application:
09/713,702 →
System and Method of Transmitting Data Frames in a Mesh of Data Switches
Patent:
6,868,071 →
Application:
09/714,382 →
Method and Apparatus for Determining and Displaying the Service Level of a Digital Television Broadcast Signal
Patent:
7,275,254 →
Application:
09/717,579 →
Method and Apparatus for Multiply-Accumulate Two-Dimensional Separable Symmetric Filtering
Patent:
6,751,640 →
Application:
09/718,877 →
Ion Implantation System
Clock Network
Extensible Bios Error Log
Alignment of Fiber Optic Bundle to Array Waveguide Using Pins
Alignment of Fiber Optic Bundle to Array Waveguide Using an Epoxy
Alignment of Optical Fibers to an Etched Array Waveguide
Method and Driver for Detecting Glitches
Method of Creating a Photonic via Using Fiber Optic
Method & Apparatus for Adding Real-Time Primitives
Markings for Aligning Fiber Optic Bundle
Metal Structure for a Phase-Change Memory Device
Novel Bi-Voltage Levels Switches
Patent:
6,522,180 →
Application:
09/745,970 →
Spindle Sleeve for Coater/Developer
Output switch for charge pump reconfiguration
Patent:
6,369,642 →
Application:
09/748,611 →
Auto Latency Test Tool
Automatic Detecting When an Agent Is Available
Matching Routed Call to Agent Workstation
Method and Apparatus for Recovery of Physical Registers During a Misprediction Condition
Voltage Level Shifter Having Zero Dc Current and State Retention in Drowsy Mode
Programmable Digital Phase Lock Loop
Clamp to Secure Carrier to Device for Electromagnetic Coupler
Method and Apparatus for Allowing Continuous Application of High Voltage to a Flash Memory Device Power Pin
Electromagnetic Coupler Socket
Triple Well No Body Effect Negative Charge Pump
Self initialization for charge pumps
Patent:
6,366,158 →
Application:
09/752,247 →
Load for Non-Volatile Memory Drain Bias
Kicker for Non-Volatile Memory Drain Bias
Method and Apparatus for Matched-Reference Sensing Architecture for Non-Volatile Memories
Method and System for Servicing Cache Line in Response to Partial Cache Line Request
System and Method for Protected Messaging
Purging Gas from a Photolithography Enclosure Between a Mask Protective Device and a Patterned Mask
Memory subsystem employing pool of refresh candidates
Patent:
6,366,516 →
Application:
09/753,005 →
Gate Enhanced Tri-Channel Positive Charge Pump
Negative output voltage charge pump and method therefor
Patent:
6,359,814 →
Application:
09/753,351 →
Multiplierless Pyramid Filter
Method and Apparatus for Compressing Calorie Burn Calculation Data Using Polynomial Coefficients
Patent:
6,689,057 →
Application:
09/773,174 →
Method and Apparatus for Detecting Ac Removal
Keyboard Holder
Initialization of Negative Charge Pump
A Method of Reducing Residue Deposition Onto Ash Chamber Base Surfaces
Method and System for Dynamic and Interactive Route Finding
Method and Apparatus for Switching an Optical Beam in a Semiconductor Substrate
Patent:
6,603,893 →
Application:
09/819,160 →
Pyramid Filter
Fastener Installation Tool
Method for Centering a Core of a Wave Guide Amplifier
Two-Dimensional Pyramid Filter Architecture
Method and Apparatus for Intersystem Cut/Copy and Paste
Dynamically Reconfigurable Optical Switching System
Patent:
6,574,386 →
Application:
09/839,848 →
Integrated Circuit Annealing Methods and Apparatus
Interconnecting Circuit Modules to a Motherboard Using an Edge Connector with Conductive Polymer Contacts
Patent:
6,461,169 →
Application:
09/849,506 →
Apparatus and Method for Removing Photomask Contamination and Controlling Electrostatic Discharge
Connector Assembly with Decoupling Capacitors
Driving a Visual Indicator Array in an Electronic Signaling System
Method and Apparatus for Utilizing Static Queues in Processor Staging
Charging a Capacitance of a Memory Cell and Charger
Parallel Cachelets
Packaging and Assembly Method for Optical Coupling
On-Die Cache Memory with Repeaters
Cascaded Domino Four-to-Two Reducer Circuit and Method
System for Sharing Channels by Interleaving Flits
Chopper Stabilized Bandgap Reference Circuit to Cancel Offset Variation
Patent:
6,462,612 →
Application:
09/894,151 →
Cache Architecture for Pipelined Operation with on-Die Processor
Cache Architecture with Redundant Sub Array
Successive Template Generation Using Minimal Random Access Memory Bandwidth
Method and Apparatus to Improve the Protection of Information Presented by a Computer
Adhesive Material for Programmable Device
Trench Sidewall Profile for Device Isolation
Dynamic Local Drive and Printer Sharing
Method for Reading a Structural Phase-Change Memory
Dynamic Delayed Transaction Buffer Configuration Based on Bus Frequency
Pcb-To-Chassis Mounting Schemes
Patent:
6,493,233 →
Application:
09/934,871 →
Voltage Driver for a Memory
Patent:
6,449,211 →
Application:
09/945,021 →
Signal to Noise Ratio Optimization for Video Compression Bit-Rate Control
Electronic Assemblies with High Capacity Curved Fin Heat Sinks
System and Method for Split Automatic Gain Control
Memory System Organized into Blocks of Different Sizes and Allocation Method Therefor
Embedded Pcb Identification
Symmetric Cascaded Domino Carry Generate Circuit
Method and Structure for Identifying Lead-Free Solder
Extension Mechanism and Method for Assembling Overhanging Components
Global I/O Timing Adjustment Using Calibrated Delay Elements
Digital Update Scheme for Adaptive Impedance Control of on-Die Input/Output Circuits
Write-Once Polymer Memory with E-Beam Writing and Reading
A Zero Insertion Force Connector for Substrates with Edge Contacts
Intelligent Forwarded Telephone Call Handling with a Call Answering System
Software Call Control Agent
Dual-Target Block Register Allocation
Removing Redundant Information in Hybrid Branch Prediction
Differential Redundancy Multiplexor for Flash Memory Devices
Method and Apparatus for Software Selection of Protected Register Settings
Method and Apparatus for Modifying Graphics Content Prior to Display for Color Blind Use
Flash Memory Program and Erase Operations
Method of Forming a Semiconductor Device Using a Carbon Doped Oxide Layer to Control the Chemical Mechanical Polishing of a Dielectric Layer
Patent:
6,548,399 →
Application:
09/996,215 →
Deferred Procedure Call in Interface Descripton Language
Portable Download Unit Including a Memory Chip-to-Cd Burner
Mechanism to Improve Authentication for Remote Management of a Computer System
Method and Apparatus for Unlocking a Computer System Hard Drive
Slurry for Polishing a Barrier Layer
Coaxial Radio Frequency Adapter and Method
1 X N Fanout Waveguide Photodetector
Look-Ahead Carry Adder Circuit
Method and Apparatus for Controlling Access to Mobile Devices
Underfill Process for Flip-Chip Device
Receiving Caller Identification Information with a Telecommunications Device for the Deaf
Patent:
6,560,317 →
Application:
10/038,411 →
Charge Pump Ripple Reduction
Property Management System Protocol Auto-Detection
Locked Content Addressable Memory for Efficient Access
Radio Frequency Amplifier with Improved Intermodulation Performance
Digital Camera with Iso Pickup Sensitivity Adjustment
Slow Motion Detection System
Inverse Multiplexing of Unmanaged Traffic Flows Over a Multi-Star Network
Common Boot Environment for a Modular Server System
Manufacturing Integrated Circuits and Testing on-Die Power Supplies Using Distributed Programmable Digital Current Sinks
Method and Apparatus for System Management Applications Using a Local Controller
Methods and Apparatus for Determining a Floating-Point Exponent Associated with an Underflow Condition or an Overflow Condition
Tunable Optical Dispersion Compensator
Patent:
6,776,493 →
Application:
10/126,106 →
Wafer-Level Test Structure for Edge-Emitting Semiconductor Lasers
Providing a Chain of Tokenized Error and State Information for a Call Stack
Rate Policing Algorithm for Packet Flows
Search Receiver Using Adaptive Detection Thresholds
Flip-Chip Package Integrating Optical and Electrical Devices and Coupling to a Waveguide on a Board
Controlling Snoop Activities Using Task Table in Multiprocessor System
Charge Pump Ripple Reduction
Method and Apparatus for Generating Gray Code for Any Even Count Value to Enable Efficient Pointer Exchange Mechanisms in Asynchronous Fifo's
Configurable Multi-Port Multi-Protocol Network Interface to Support Packet Processing
Speed Control Playback of Parametric Speech Encoded Digital Audio
Test Interface, System, and Method for Testing Communications Devices with Non-Deterministic Latency
Method, System, and Program for Memory Based Data Transfer
Dynamic Power Level Control Based on a Board Latch State
Practical Coding and Metric Calculation for the Lattice Interfered Channel
Data Packet Header Conversion
Voltage Controlled Oscillators
Multi-Die Semiconductor Package
Method for Packaging a Tape Substrate
Slave I/O Driver Calibration Using Error-Nulling Master Reference
Dielectric Material Treatment
Deterministic Bandwidth Throttling to Facilitate Operation of a Control Unit
Updating Stack Pointer Based on Instruction Bit Indicator Without Executing an Update Microinstruction
Generating Animation from Visual and Audio Input
Method and Apparatus for Independent Control of Devices Under Test Connected in Parallel
Methods and Apparatus for Configuring Hardware Resources in a Pre-Boot Environment Without Requiring a System Reset
Efficient Echo Cancellation Techniques
Photoactive Adhesion Promoter
Portable Computing Device Adapted to Update Display Information While in a Low Power Mode
Apparatus and Method for Time Synchronization of a Plurality of Multimedia Streams
Methods and Apparatuses Using a Fiber-Flexure Induction Soldering Station
Methods to Pattern Contacts Using Chromeless Phase Shift Masks
Automatic Symbolic Indexing Methods for Formal Verification on a Symbolic Lattice Domain
Stimulus Generation
Method and Apparatus for Laser Annealing
Electronic Packages and Components Thereof Formed by Substrate-Imprinting
Mechanism to Guarantee Forward Progress for Incoming Coherent Input/Output (I/O) Transactions for Caching I/O Agent on Address Conflict with Processor Transactions
Electrostatic Discharge Protection Unit Including Equalization
On-Chip Jitter Testing
System and Method to Analyze Vlsi Designs
Optical Thumbtack
Venting of Pellicle Cavity for a Mask
Optical Storage Transfer Performance
Variable Latch
Reusable, Built-in Self-Test Methodology for Computer Systems
Apparatus and Method for Combining Writes to I/O
Push Button Mode Automatic Pattern Switching for Interconnect Built-in Self Test
Leakage Control in Integrated Circuits
System and Method to Initialize Registers with an Eeprom Stored Boot Sequence
Test Scan Cells
Pcb Design and Method for Providing Vented Blind Vias
Patent:
6,787,443 →
Application:
10/442,834 →
Oscillator System with Switched-Capacitor Network and Method for Generating a Precision Time Reference
Dynamic Bios Execution and Concurrent Update for a Blade Server
Method and Process for Determining a Quotient
Future Activity List for Peripheral Bus Host Controller
Timing Analysis Apparatus, Systems, and Methods
Electrical Device Connector
Method and Apparatus to Create Bypass Logic in a Digital Circuit Design
Elimination of Potential Renaming Stalls Due to Use of Partial Registers
Apparatus, System and Method for Updating a Sorted List
Method and Apparatus for Integrated Circuit Self-Description
Apparatus for Precise Alignment of Packaging Caps on a Substrate
Inkjet printing system with an intermediate transfer member between the print engine and print medium
Application:
10/611,738 →
Publication:
US 2004/0095452
Bond Finger on via Substrate, Process of Making Same, Package Made Thereby, and Method of Assembling Same
Selective Control of Test-Access Ports in Integrated Circuits
Network Statistics
Systems and Methods for Using Hdlc Channel Context to Simultaneously Process Multiple Hdlc Channels
Prioritized Address Decoder
Method and Apparatus for Trusted Keyboard Scanning
Method and Apparatus for Integrated Circuit Datapath Layout Using a Vector Editor
Passing Parameters by Implicit Reference
Modified Electroplating Solution Components in a Low-Acid Electrolyte Solution
Method and Apparatus for Limiting Ports in a Register Alias Table Having High-Bandwidth and Low-Bandwidth Structures
Symbolic Buffer Allocation in Local Cache at a Network Processing Element
Smaller and Lower Power Static Mux Circuitry in Generating Multiplier Partial Product Signals
Method and Apparatus for Prediction for Fork and Join Instructions in Speculative Execution
Secure Booting and Provisioning
Predictive Filtering of Register Cache Entry
Method and Apparatus for Dedicating Cache Entries to Certain Streams for Performance Optimization
Method and Apparatus to Manage Exceptions in Network Processors
Queue Structure with Validity Vector and Order Array
Interconnect Structure in Integrated Circuits
Electromagnetic Interference (Emi) Filter with Passive Noise Cancelation
Method, System, and Apparatus for Tracking Defective Cache Lines
Print Stripper for Esd Control
Processing Replies to Request Packets in an Advanced Switching Context
Training Pattern Based De-Skew Mechanism and Frame Alignment
Device and Methods for Increasing Wireless Connection Speeds
Power Distribution Within a Folded Flex Package Method and Apparatus
Programmable Power Transition Counter
Method and Apparatus for Providing a Connection Matrix
Patent:
7,512,060 →
Application:
11/015,967 →
Scalable Traceback Technique for Channel Decoder
Low-Swing Level Shifter
Methods to Perform Cache Coherency in Multiprocessor System Using Reserve Signals and Control Bits
Flash Memory Cell Having Reduced Floating Gate to Floating Gate Coupling
Wireless Device Enclosure Using Piezoelectric Cooling Structures
Voltage Controlled Oscillator (Vco) Tuning
Apparatus, System, and Method for Oscillator Network with Multiple Parallel Oscillator Circuits
Dc-Dc Converter Switching Transistor Current Measurement Technique
Memory Controller Hub Interface
Universal Nonvolatile Memory Boot Mode
Power Loss Recovery in Non-Volatile Memory
Method and Apparatus for Optimizing Flash Device Erase Distribution
Processor Multi-Partition Security Architecture
Structured, Electrically-Formed Floating Gate for Flash Memories
A Host Computer Using Basic Input and Output System to Process Control Command Received from a Remote Computer According to Timer Interrupts
A System Processing Data Packets Received from Remote Host to Control System Operation According to Adjustable Timer Interrupts Based on Data Flow Rate
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Patent Security Agreement
Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
Corrective Assignment to Correct the Replace Erroneously Filed Patent #7358718 with the Correct Patent #7358178 Previously Recorded on Reel 038669 Frame 0001. Assignor(S) Hereby Confirms the Security Interest.
Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →