Predictive filtering of register cache entry
View Patent ↗A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.
1. A method, comprising:
monitoring at least one waiting instruction in an instruction window, wherein the waiting instruction includes a reference to a physical register;
incrementing a reference count for said physical register based on said reference;
utilizing said reference count to determine the potential significance of data in said physical register to future instructions; and
entering said data into at least one register cache according to said potential significance.
2. The method of claim 1 , further comprising:
incrementing said reference count once for each additional reference to said physical register in the instruction window.
3. The method of claim 1 , wherein said entering said data is conditional on said potential significance being high.
4. The method of claim 1 , wherein said entering said data is conditional on said potential significance being low.
5. The method of claim 1 , wherein said entering further comprises inserting data into an empty slot in said at least one register cache.
6. The method of claim 1 , further comprising:
selecting previous data from a slot in said at least one register cache according to the potential significance of said previous data; and
evicting said previous data from said slot in said at least one register cache prior to said inserting said data.
7. The method of claim 1 , wherein:
said waiting instruction includes a reference to a second physical register; and
said incrementing further comprises incrementing a second reference count for said second physical register based on said reference to the second physical register.
8. The method of claim 1 , wherein:
said utilizing is performed responsive to a demand miss.
9. An apparatus, comprising:
one or more physical registers to store data associated with a plurality of instructions;
an instruction window to hold the plurality of instructions, the plurality of instructions including at least one waiting instruction whose data is not yet available in the physical registers;
a counter look-up table to track the number of references to each of said one or more physical registers in the instruction window;
a reference count circuit to determine a potential significance for data of said one or more physical registers based on said number of references; and
at least one register cache, wherein said reference count circuit is to enter said data into said at least one register cache according to said potential significance.
10. The apparatus of claim 9 , wherein at least one register cache, wherein said reference count circuit is further to enter said data of said one or more physical registers into said at least one register cache according to said potential significance.
11. The apparatus of claim 9 , wherein said reference count circuit is to enter said data when said potential significance is high.
12. The apparatus of claim 9 , wherein said reference count circuit is to insert said data when said potential significance is low.
13. The apparatus of claim 9 , wherein said reference count circuit is to insert said data into an empty slot in said at least one register cache.
14. The apparatus of claim 9 , wherein said reference count circuit is to select and evict previous data from a slot in said at least one register cache according to a potential significance of said previous data prior to inserting said data.
15. The apparatus of claim 9 , said counter look-up table further comprising:
at least one physical register identifier; and
at least one counter associated with said physical register identifier, wherein said at least one counter is to indicate the number of references to said physical register in the instructions of the instruction window.
16. The apparatus of claim 15 , wherein said reference count circuit is further to increment the counter for each of said references.
17. A system, comprising:
a processor including an instruction window to hold a plurality of instructions, the plurality to include at least one future instruction, one or more physical registers to store data associated with said at least one future instruction, a counter look-up table to track one or more physical register references in the instruction window to said one or more physical registers, a reference count circuit to determine a potential significance for data of said one or more physical registers based on said physical register references, and at least one register cache, wherein said reference count circuit is to enter said data into said at least one register cache according to said potential significance;
an interface to couple said processor to input-output devices; and
a data storage coupled to said interface to receive code from said processor.
18. The system of claim 17 , wherein said reference count circuit is to enter said data of said one or more physical registers into said at least one register cache according to said potential significance to the plurality of instructions in the instruction window, including to said future instruction.
19. The system of claim 17 , wherein said reference count circuit is to enter said data responsive to said potential significance being high.
20. The system of claim 17 , wherein said reference count circuit is to enter said data responsive to said potential significance being low.
21. The system of claim 17 , wherein said reference count circuit is further to enter said data into an empty slot in said at least one register cache.
22. The system of claim 17 , wherein said reference count circuit is further to select and evict previous data from a slot in said at least one register cache according to a potential significance of said previous data prior to inserting said data.
23. The system of claim 17 , further comprising:
one or more additional physical registers to store data associated with the plurality of instructions;
wherein said counter look-up table is further to track one or more physical register references in the instruction window to said additional physical registers.
24. The system of claim 17 , wherein said reference count circuit is further to increment said counter for each of said at least one physical register references.